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? 2008-2013 microchip technology inc. ds22096b-page 1 mcp453x/455x/463x/465x features: single or dual resistor network options potentiometer or rheostat configuration options resistor network resolution - 7-bit: 128 resistors (129 steps) - 8-bit: 256 resistors (257 steps) r ab resistances options of: -5k ? -10k ? -50k ? -100k ? zero-scale to full-scale wiper operation low wiper resistance: 75 ? (typical) low tempco: - absolute (rheostat): 50 ppm typical (0c to 70c) - ratiometric (potentiometer): 15 ppm typical i 2 c serial interface - 100 khz, 400 khz and 3.4 mhz support serial protocol allows: - high-speed read/write to wiper - increment/decrement of wiper resistor network terminal disconnect feature via the terminal control (tcon) register brown-out reset protection (1.5v typical) serial interface inactive current (2.5 ua typical) high-voltage tolerant digital inputs: up to 12.5v wide operating voltage: - 2.7v to 5.5v - device characteristics specified - 1.8v to 5.5v - device operation wide bandwidth (-3db) operation: - 2 mhz (typical) for 5.0 k ? device extended temperature range (-40c to +125c) description: the mcp45xx and mcp46xx devices offer a wide range of product offerings using an i 2 c interface. this family of devices support 7-bit and 8-bit resistor networks, volatile memory configurations, and potentiometer and rheostat pinouts. package types (top view) 12 3 4 5 6 7 8 p0w p0b p0a v ss v dd mcp45x1 single potentiometer msop hvc / a0 sda scl 12 3 4 5 6 7 8 p0b a1 p0w v dd msop 12 3 4 11 12 13 14 a2 a1nc v dd mcp46x1 dual potentiometers tssop 56 7 8 9 10 p0w p0b p0a p1a p1w p1b v ss hvc / a0 sda scl v ss hvc/a0 sda scl qfn-16 4x4 (ml) * mcp46x2 dual rheostat msop mcp45x2 single rheostat dfn 3x3 (mf) * dfn 3x3 (mf) * sda scl v ss a1p0b 1 2 3 4 8 7 6 5 p0w v dd hvc / a0 * includes exposed t hermal pad (ep); see table 3-1 . ep 9 dfn 3x3 (mf) * sda scl v ss p0b p0w 1 2 3 4 8 7 6 5 p0a v dd hvc / a0 ep 9 2 v ss v ss scl nc nc p1b p0b p1w p1a p0a p0w hvc/a0 v dd a1a2 sda ep 16 1 15 14 13 34 12 11 10 9 5678 17 sda scl v ss a1p0b 1 2 3 4 10 9 8 7 p0w v dd hvc / a0 ep 11 p1b 5 6 p1w 12 3 4 7 8 9 10 a1 v dd 5 6 p0b p0w p1w p1b v ss hvc/a0 sda scl 7/8-bit single/dual i 2 c digital pot with volatile memory downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 2 ? 2008-2013 microchip technology inc. device block diagram device features device # of pots wiper configuration control memory type wiperlock por wiper setting resistance (typical) # of steps v dd operating range ( 2 ) r ab options (k ? ) wiper - r w ( ? ) mcp4531 1 potentiometer ( 1 ) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4532 1 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4541 1 potentiometer ( 1 ) i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4542 1 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4551 1 potentiometer ( 1 ) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4552 1 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4561 1 potentiometer ( 1 ) i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v mcp4562 1 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v mcp4631 2 potentiometer ( 1 ) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4632 2 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4641 2 potentiometer ( 1 ) i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4642 2 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7v to 5.5v mcp4651 2 potentiometer ( 1 ) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4652 2 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4661 2 potentiometer ( 1 ) i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v mcp4662 2 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7v to 5.5v note 1: floating either terminal (a or b) allows the device to be used as a rheostat (variable resistor). 2: analog characteristics only tested from 2.7v to 5.5v unless otherwise noted. power-up/ brown-out control v dd v ss i 2 c serial interface module & control logic (wiperlock? te ch no l og y) resistor network 0 (pot 0) wiper 0 & tcon register resistor network 1 (pot 1) wiper 1 & tcon register a2 a1 hvc/a0 scl sda memory (16x9) wiper0 (v) wiper1 (v) tcon reserved p0a p0w p0b p1a p1w p1b for dual resistor network devices only i 2 c interface downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 3 mcp453x/455x/463x/465x 1.0 electrical characteristics absolute maximum ratings ? voltage on v dd with respect to v ss .......................................................................................................... -0.6v to +7.0v voltage on hvc/a0, a1, a2, scl, and sda with respect to v ss ............................................................................. -0.6v to 12.5v voltage on all other pins (pxa, pxw, and pxb) with respect to v ss ............................................................. -0.3v to v dd + 0.3v input clamp current, i ik (v i < 0, v i > v dd , v i > v pp on hv pins)........................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ...................................................................................................20 ma maximum output current sunk by any output pin.................................................................................. ..................25 ma maximum output current sourced by any output pin ............................................................................... ...............25 ma maximum current out of v ss pin ........................................................................................................................... 100 ma maximum current into v dd pin ........................................................................................................................... ...100 ma maximum current into p x a, p x w & p x b pins ...................................................................................................... 2.5 ma storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied......................................................................................... .......-40c to +125c package power dissipation (t a = +50c, t j = +150c) mssop-8 .................................................................................................................. .....................................473 mw mssop-8 ........................................................................................................................ ...............................473 mw mssop-10 ................................................................................................................. ....................................495 mw dfn-8 (3x3) .............................................................................................................. ........................................1.76w dfn-10 (3x3) ............................................................................................................. .......................................1.87w tssop-14................................................................................................................. ........................................1.00w qfn-16 (4x4) ............................................................................................................. .......................................2.18w soldering temperature of leads (10 seconds) .................................................................................... ................... +300c esd protection on all pins ???????????????????????????????????????????????????????????????????????????????????????????????????? ???????????????????????????????????? ?? 4 kv (hbm) ???????????????????????????????????????????????????????????????????????????????????????????????????? ?????????????????????????????????????????????????????????????????????????????????????? 300v (mm) maximum junction temperature (t j ) ................................................................................................................... +150c ? notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended peri- ods may affect device reliability. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 4 ? 2008-2013 microchip technology inc. ac/dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions supply voltage v dd 2.7 5.5 v 1.8 2.7 v serial interface only. hvc pin voltage range v hv v ss 12 .5v v v dd ? 4.5v the hvc pin will be at one of three input levels (v il , v ih or v ihh ). ( note 6 ) v ss v dd + 8.0v vv dd < 4.5v v dd start voltage to ensure wiper reset v bor 1.65 v ram retention voltage (v ram ) < v bor v dd rise rate to ensure power-on reset v ddrr ( note 9 )v / m s delay after device exits the reset state (v dd > v bor ) t bord 1 02 0 s supply current ? ( note 10 ) i dd 600 a serial interface active, hvc/a0 = v ih (or v il ) ( note 11 ) write all 0s to volatile wiper 0 v dd = 5.5v, f scl = 3.4 mhz 250 a serial interface active, hvc/a0 = v ih (or v il ) ( note 11 ) write all 0s to volatile wiper 0 v dd = 5.5v, f scl = 100 khz 2.5 5 a serial interface inactive, (stop condition, scl = sda = v ih ), wiper = 0 v dd = 5.5v, hvc/a0 = v ih note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 5 mcp453x/455x/463x/465x resistance ( 20%) r ab 4.0 5 6.0 k ? -502 devices ? ( note 1 ) 8.0 10 12.0 k ? -103 devices ? ( note 1 ) 40.0 50 60.0 k ? -503 devices ? ( note 1 ) 80.0 100 120.0 k ? -104 devices ? ( note 1 ) resolution n 257 taps 8-bit no missing codes 129 taps 7-bit no missing codes step resistance r s r ab / (256) ? 8-bit note 6 r ab / (128) ? 7-bit note 6 nominal resistance match |r ab0 -r ab1 | /r ab 0 . 21 . 2 5% mcp46x1 devices only |r bw0 -r bw1 | /r bw 0.25 1.5 % mcp46x2 devices only, code = full-scale wiper resistance ( note 3 , note 4 ) r w 75 160 ? v dd = 5.5 v, i w = 2.0 ma, code = 00h 75 300 ? v dd = 2.7 v, i w = 2.0 ma, code = 00h nominal resistance te m p c o ? r ab / ? t 50 ppm/c t a = -20c to +70c 1 0 0p p m / c t a = -40c to +85c 1 5 0p p m / c t a = -40c to +125c ratiometeric te m p c o ? v wb / ? t 15 ppm/c code = midscale (80h or 40h) resistor terminal input voltage range (terminals a, b and w) v a, v w, v b vss v dd v note 5 , note 6 ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 6 ? 2008-2013 microchip technology inc. maximum current through terminal (a, w or b) note 6 i t 2.5 ma terminal a i aw , w = full-scale (fs) 2.5 ma terminal b i bw , w = zero scale (zs) 2.5 ma terminal w i aw or i bw , w = fs or zs 1 . 3 8m a te r m i n a l a and te r m i n a l b i ab , v b = 0v, v a = 5.5v, r ab(min) = 4000 0.688 ma i ab , v b = 0v, v a = 5.5v, r ab(min) = 8000 0.138 ma i ab , v b = 0v, v a = 5.5v, r ab(min) = 40000 0.069 ma i ab , v b = 0v, v a = 5.5v, r ab(min) = 80000 leakage current into a, w or b i wl 1 0 0n a mcp4xx1 pxa = pxw = pxb = v ss 1 0 0n a mcp4xx2 pxb = pxw = v ss 100 na terminals disconnected (r1hw = r0hw = 0) ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 7 mcp453x/455x/463x/465x full-scale error ( mcp4xx1 only) (8-bit code = 100h, 7-bit code = 80h) v wfse -6.0 -0.1 lsb 5 k ? 8-bit 3.0v ? v dd ? 5.5v -4.0 -0.1 lsb 7-bit 3.0v ? v dd ? 5.5v -3.5 -0.1 lsb 10 k ? 8-bit 3.0v ? v dd ? 5.5v -2.0 -0.1 lsb 7-bit 3.0v ? v dd ? 5.5v -0.8 -0.1 lsb 50 k ? 8-bit 3.0v ? v dd ? 5.5v -0.5 -0.1 lsb 7-bit 3.0v ? v dd ? 5.5v -0.5 -0.1 lsb 100 k ? 8-bit 3.0v ? v dd ? 5.5v -0.5 -0.1 lsb 7-bit 3.0v ? v dd ? 5.5v zero-scale error ( mcp4xx1 only) (8-bit code = 00h, 7-bit code = 00h) v wzse + 0 . 1+ 6 . 0l s b5 k ? 8-bit 3.0v ? v dd ? 5.5v +0.1 +3.0 lsb 7-bit 3.0v ? v dd ? 5.5v +0.1 +3.5 lsb 10 k ? 8-bit 3.0v ? v dd ? 5.5v +0.1 +2.0 lsb 7-bit 3.0v ? v dd ? 5.5v +0.1 +0.8 lsb 50 k ? 8-bit 3.0v ? v dd ? 5.5v +0.1 +0.5 lsb 7-bit 3.0v ? v dd ? 5.5v +0.1 +0.5 lsb 100 k ? 8-bit 3.0v ? v dd ? 5.5v +0.1 +0.5 lsb 7-bit 3.0v ? v dd ? 5.5v potentiometer integral non-linearity inl -1 0.5 +1 lsb 8-bit 3.0v ? v dd ? 5.5v mcp4xx1 devices only ( note 2 ) -0.5 0.25 +0.5 lsb 7-bit potentiometer differential non-linearity dnl -0.5 0.25 +0.5 lsb 8-bit 3.0v ? v dd ? 5.5v mcp4xx1 devices only ( note 2 ) -0.25 0.125 +0.25 lsb 7-bit ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 8 ? 2008-2013 microchip technology inc. bandwidth -3 db (see figure 2-65 , load = 30 pf) bw 2 mhz 5 k ? 8-bit code = 80h 2 mhz 7-bit code = 40h 1m h z 1 0 k ? 8-bit code = 80h 1 mhz 7-bit code = 40h 2 0 0k h z5 0 k ? 8-bit code = 80h 200 khz 7-bit code = 40h 100 khz 100 k ? 8-bit code = 80h 100 khz 7-bit code = 40h ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 9 mcp453x/455x/463x/465x rheostat integral non-linearity mcp45x1 ( note 4 , note 8 ) mcp4xx2 devices only ( note 4 ) r-inl -1.5 0.5 +1.5 lsb 5 k ? 8-bit 5.5v, i w = 900 a -8.25 +4.5 +8.25 lsb 3.0v, i w = 480 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 900 a -6.0 +4.5 +6.0 lsb 3.0v, i w = 480 a ( note 7 ) -1.5 0.5 +1.5 lsb 10 k ? 8-bit 5.5v, i w = 450 a -5.5 +2.5 +5.5 lsb 3.0v, i w = 240 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 450 a -4.0 +2.5 +4.0 lsb 3.0v, i w = 240 a ( note 7 ) -1.5 0.5 +1.5 lsb 50 k ? 8-bit 5.5v, i w = 90 a -2.0 +1 +2.0 lsb 3.0v, i w = 48 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 90 a -1.5 +1 +1.5 lsb 3.0v, i w = 48 a ( note 7 ) -1.0 0.5 +1.0 lsb 100 k ? 8-bit 5.5v, i w = 45 a -1.5 +0.25 +1.5 lsb 3.0v, i w = 24 a ( note 7 ) -0.8 0.5 +0.8 lsb 7-bit 5.5v, i w = 45 a -1.125 +0.25 +1.125 lsb 3.0v, i w = 24 a ( note 7 ) ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 10 ? 2008-2013 microchip technology inc. rheostat differential non-linearity mcp45x1 ( note 4 , note 8 ) mcp4xx2 devices only ( note 4 ) r-dnl -0.5 0.25 +0.5 lsb 5 k ? 8-bit 5.5v, i w = 900 a -1.0 +0.5 +1.0 lsb 3.0v, i w = 480 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 900 a -0.75 +0.5 +0.75 lsb 3.0v, i w = 480 a ( note 7 ) -0.5 0.25 +0.5 lsb 10 k ? 8-bit 5.5v, i w = 450 a -1.0 +0.25 +1.0 lsb 3.0v, i w = 240 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 450 a -0.75 +0.5 +0.75 lsb 3.0v, i w = 240 a ( note 7 ) -0.5 0.25 +0.5 lsb 50 k ? 8-bit 5.5v, i w = 90 a -0.5 0.25 +0.5 lsb 3.0v, i w = 48 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 90 a -0.375 0.25 +0.375 lsb 3.0v, i w = 48 a ( note 7 ) -0.5 0.25 +0.5 lsb 100 k ? 8-bit 5.5v, i w = 45 a -0.5 0.25 +0.5 lsb 3.0v, i w = 24 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 45 a -0.375 0.25 +0.375 lsb 3.0v, i w = 24 a ( note 7 ) capacitance (p a )c aw 75 pf f =1 mhz, code = full-scale capacitance (p w )c w 120 pf f =1 mhz, code = full-scale capacitance (p b )c bw 75 pf f =1 mhz, code = full-scale ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 11 mcp453x/455x/463x/465x digital inputs/outputs (sda, sck, hvc/a0, a1, a2, wp ) schmitt trigger high input threshold v ih 0.45 v dd v a l l inputs except sda and scl 2.7v ? v dd ? 5.5v (allows 2.7v digital v dd with 5v analog v dd ) 0.5 v dd v 1 . 8 v ? v dd ? 2.7v 0.7 v dd v max v sda and scl 100 khz 0.7 v dd v max v4 0 0 k h z 0.7 v dd v max v1 . 7 m h z 0.7 v dd v max v3 . 4 m h z schmitt trigger low input threshold v il 0.2v dd v all inputs except sda and scl -0.5 0.3v dd v sda and scl 100 khz -0.5 0.3v dd v4 0 0 k h z -0.5 0.3v dd v1 . 7 m h z -0.5 0.3v dd v3 . 4 m h z hysteresis of schmitt trigger inputs ( note 6 ) v hys 0 . 1 v d d v all inputs except sda and scl n.a. v sda and scl 100 khz v dd < 2.0v n.a. v v dd ? 2.0v 0.1 v dd v 400 khz v dd < 2.0v 0.05 v dd v v dd ? 2.0v 0.1 v dd v 1 . 7 m h z 0.1 v dd v 3 . 4 m h z high voltage limit v max 1 2 . 5 ( 6 ) v pin can tolerate v max or less. ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 12 ? 2008-2013 microchip technology inc. figure 1-1: i 2 c bus start/stop bits timing waveforms. output low voltage (sda) v ol v ss 0.2v dd vv dd < 2.0v, i ol = 1 ma v ss 0 . 4 vv dd ? 2.0v, i ol = 3 ma weak pull-up / pull-down current i pu 1.75 ma internal v dd pull-up, v ihh pull-down v dd = 5.5v, v ihh = 12.5v 170 a hvc pin, v dd = 5.5v, v hvc = 3v hvc pull-up / pull-down resistance r hvc 1 6k ? v dd = 5.5v, v hvc = 3v input leakage current i il -1 1 a v in = v dd and v in = v ss pin capacitance c in , c out 1 0p ff c = 3.4 mhz ram (wiper) value value range n 0h 1ffh hex 8-bit device 0h 1ffh hex 7-bit device tcon por/bor value n tcon 1ffh hex all terminals connected power requirements power supply sensitivity ( mcp45x2 and mcp46x2 only) pss 0.0015 0.0035 %/% 8-bit v dd = 2.7v to 5.5v, v a = 2.7v, code = 80h 0.0015 0.0035 %/% 7-bit v dd = 2.7v to 5.5v, v a = 2.7v, code = 40h ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k ? , 10 k ? , 50 k ? , 100 k ? devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and bs polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes significantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network. 11: when hvc/a0 = v ihh , the i dd current is less due to current into the hvc/a0 pin. see i pu specification. 91 93 scl sda start condition stop condition 90 92 downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 13 mcp453x/455x/463x/465x table 1-1: i 2 c bus start/stop bits requirements figure 1-2: i 2 c bus data timing. i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature C40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. symbol characteristic min max units conditions f scl standard mode 0 100 khz c b = 400 pf, 1.8v - 5.5v fast mode 0 400 khz c b = 400 pf, 2.7v - 5.5v high-speed 1.7 0 1.7 mhz c b = 400 pf, 4.5v - 5.5v high-speed 3.4 0 3.4 mhz c b = 100 pf, 4.5v - 5.5v d102 c b bus capacitive loading 100 khz mode 400 pf 400 khz mode 400 pf 1.7 mhz mode 400 pf 3.4 mhz mode 100 pf 90 t su:sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 ns 1.7 mhz mode 160 ns 3.4 mhz mode 160 ns 91 t hd:sta start condition 100 khz mode 4000 ns after this period the first clock pulse is generated hold time 400 khz mode 600 ns 1.7 mhz mode 160 ns 3.4 mhz mode 160 ns 92 t su:sto stop condition 100 khz mode 4000 ns setup time 400 khz mode 600 ns 1.7 mhz mode 160 ns 3.4 mhz mode 160 ns 93 t hd:sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 ns 1.7 mhz mode 160 ns 3.4 mhz mode 160 ns 90 91 92 100 101 103 106 107 109 109 110 102 scl sdain sda out downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 14 ? 2008-2013 microchip technology inc. table 1-2: i 2 c bus data requirements (slave mode) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature C40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4000 ns 1.8v-5.5v 400 khz mode 600 ns 2.7v-5.5v 1.7 mhz mode 120 ns 4.5v-5.5v 3.4 mhz mode 60 ns 4.5v-5.5v 101 t low clock low time 100 khz mode 4700 ns 1.8v-5.5v 400 khz mode 1300 ns 2.7v-5.5v 1.7 mhz mode 320 ns 4.5v-5.5v 3.4 mhz mode 160 ns 4.5v-5.5v 102a ( note 5 ) t rscl scl rise time 100 khz mode 1000 ns cb is specified to be from 10 to 400 pf (100 pf maximum for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 80 ns 1.7 mhz mode 20 160 ns after a repeated start condition or an acknowledge bit 3.4 mhz mode 10 40 ns 3.4 mhz mode 10 80 ns after a repeated start condition or an acknowledge bit 102b ( note 5 ) t rsda sda rise time 100 khz mode 1000 ns cb is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns 103a ( note 5 ) t fscl scl fall time 100 khz mode 300 ns cb is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 80 ns 3.4 mhz mode 10 40 ns note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: use c b in pf for the calculations. 4: not tested. 5: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. 6: ensured by the t aa 3.4 mhz specification test. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 15 mcp453x/455x/463x/465x 103b ( note 5 ) t fsda sda fall time 100 khz mode 300 ns cb is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb ( note 3 ) 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns 106 t hd:dat data input hold time 100 khz mode 0 ns 1.8v-5.5v, note 5 400 khz mode 0 ns 2.7v-5.5v, note 5 1.7 mhz mode 0 ns 4.5v-5.5v, note 5 3.4 mhz mode 0 ns 4.5v-5.5v, note 5 107 t su:dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 1.7 mhz mode 10 ns 3.4 mhz mode 10 ns 109 t aa output valid from clock 100 khz mode 3450 ns note 1 400 khz mode 900 ns 1.7 mhz mode 150 ns cb = 100 pf, note 1 , note 6 310 ns cb = 400 pf, note 1 , note 4 3.4 mhz mode 150 ns cb = 100 pf, note 1 110 t buf bus free time 100 khz mode 4700 ns time the bus must be free before a new transmission can start 400 khz mode 1300 ns 1.7 mhz mode n.a. ns 3.4 mhz mode n.a. ns t sp input filter spike suppression (sda and scl) 100 khz mode 50 ns philips spec states n.a. 400 khz mode 50 ns 1.7 mhz mode 10 ns spike suppression 3.4 mhz mode 10 ns spike suppression table 1-2: i 2 c bus data requirements (slave mode) (continued) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature C40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. symbol characteristic min max units conditions note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl si gnal, it must output the next data bit to the sda line. t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: use c b in pf for the calculations. 4: not tested. 5: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. 6: ensured by the t aa 3.4 mhz specification test. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 16 ? 2008-2013 microchip technology inc. temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 +125 c operating temperature range t a -40 +125 c storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 8l-dfn (3x3) ? ja 5 6 . 7 c / w thermal resistance, 8l-msop ? ja 2 1 1 c / w thermal resistance, 8l-soic ? ja 149.5 c/w thermal resistance, 10l-dfn (3x3) ? ja 5 7 c / w thermal resistance, 10l-msop ? ja 2 0 2 c / w thermal resistance, 14l-msop ? ja n / a c / w thermal resistance, 14l-soic ? ja 9 5 . 3 c / w thermal resistance, 16l-qfn ? ja 4 5 . 7 c / w downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 17 mcp453x/455x/463x/465x 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-1: device current (i dd ) vs. i 2 c frequency (f scl ) and ambient temperature (v dd = 2.7v and 5.5v). figure 2-2: device current (i shdn ) and v dd (hvc = v dd ) vs. ambient temperature. figure 2-3: write current (i write ) vs. ambient temperature. figure 2-4: hvc pull-up/pull-down resistance (r hvc ) and current (i hvc ) vs. hvc input voltage (v hvc ) (v dd = 5.5v). figure 2-5: hvc high input entry/exit threshold vs. ambient temperature and v dd . note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0 100 200 300 400 500 600 700 800 -40 0 40 80 120 temperature (c) i dd (a) 100 khz, 5.5v 400 khz, 5.5v 1.7 mhz, 5.5v 3.4 mhz, 5.5v 100 khz, 2.7v 400 khz, 2.7v 1.7 mhz, 4.5v 3.4 mhz, 4.5v 0.5 1 1.5 2 2.5 3 -40 0 40 80 120 temperature (c) istandby (a) 5.5v 2.7v 300 320 340 360 380 400 420 -40 0 40 80 120 temperature (c) i write (a) 5.5v 0 50 100 150 200 250 2345678910 v hvc (v) r hvc (kohms) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 i hvc (a) i hvc r hvc 0 2 4 6 8 10 12 -40-200 20406080100120 ambient temperature (c) hvc v pp threshold (v) 2.7v exit 5.5v exit 2.7v entry 5.5v entry downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 18 ? 2008-2013 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-6: 5k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-7: 5k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-8: 5k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 1.8v). figure 2-9: 5k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-10: 5k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-11: 5k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 1.8v). 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl -40c 25c 85c r w 125c 0 500 1000 1500 2000 2500 0 64 128 192 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw note: refer to appendix b: ?characteriza- tion data analysis? for additional infor- mation on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1.25 -0.75 -0.25 0.25 0.75 1.25 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 0 2 4 6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 500 1000 1500 2000 2500 0 64 128 192 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 18 38 58 78 98 118 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw note: refer to appendix b: ?characteriza- tion data analysis? for additional infor- mation on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 19 mcp453x/455x/463x/465x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-12: 5k ? ? nominal resistance ( ? ) vs. ambient temperature and v dd . figure 2-13: 5k ? ? r wb ( ? ) vs. wiper setting and ambient temperature. 5050 5100 5150 5200 5250 5300 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 1.8v 0 1000 2000 3000 4000 5000 6000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 20 ? 2008-2013 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-14: 5k ? ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-15: 5k ? ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-16: 5k ? ? power-up wiper response time (20 ms/div). figure 2-17: 5k ? ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div). figure 2-18: 5k ? ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 21 mcp453x/455x/463x/465x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-19: 10 k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-20: 10 k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-21: 10 k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 1.8v). figure 2-22: 10 k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-23: 10 k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-24: 10 k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 1.8v). 20 40 60 80 100 120 0 25 50 75 100 125 150 175 200 225 250 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 500 1000 1500 2000 2500 3000 3500 4000 0 64 128 192 256 wiper setting (decimal) wiper resistance (r w )(ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw note: refer to appendix b: ?characteriza- tion data analysis? for additional infor- mation on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 -0.5 0 0.5 1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 25 50 75 100 125 150 175 200 225 250 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 -1 0 1 2 3 4 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 500 1000 1500 2000 2500 3000 3500 4000 06 41 2 81 9 22 5 6 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 8 18 28 38 48 58 68 78 88 98 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw note: refer to appendix b: ?characteriza- tion data analysis? for additional infor- mation on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 22 ? 2008-2013 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-25: 10 k ? ? nominal resistance ( ? ) vs. ambient temperature and v dd . figure 2-26: 10 k ? ? r wb ( ? ) vs. wiper setting and ambient temperature. 9850 9900 9950 10000 10050 10100 10150 10200 10250 10300 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 1.8v 0 2000 4000 6000 8000 10000 12000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 23 mcp453x/455x/463x/465x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-27: 10 k ? ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-28: 10 k ? ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-29: 10 k ? ? power-up wiper response time (1 s/div). figure 2-30: 10 k ? ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div). figure 2-31: 10 k ? ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 24 ? 2008-2013 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-32: 50 k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-33: 50 k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-34: 50 k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 1.8v). figure 2-35: 50 k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-36: 50 k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-37: 50 k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 1.8v). 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 13000 14000 15000 0 64 128 192 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw note: refer to appendix b: ?characteriza- tion data analysis? for additional infor- mation on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 13000 14000 15000 0 25 50 75 100 125 150 175 200 225 250 wiper setting (decimal) wiper resistance (rw) (ohms) -1.5 3.5 8.5 13.5 18.5 23.5 28.5 33.5 38.5 43.5 48.5 53.5 58.5 63.5 68.5 73.5 78.5 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw note: refer to appendix b: ?characteriza- tion data analysis? for additional infor- mation on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 25 mcp453x/455x/463x/465x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-38: 50 k ? ? nominal resistance ( ? ) vs. ambient temperature and v dd . figure 2-39: 50 k ? ? r wb ( ? ) vs. wiper setting and ambient temperature. 49000 49500 50000 50500 51000 51500 52000 52500 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 1.8v 5.5v 0 10000 20000 30000 40000 50000 60000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 26 ? 2008-2013 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-40: 50 k ? ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-41: 50 k ? ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-42: 50 k ? ? power-up wiper response time (1 s/div). figure 2-43: 50 k ? ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div). figure 2-44: 50 k ? ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 27 mcp453x/455x/463x/465x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-45: 100 k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-46: 100 k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-47: 100 k ? pot mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 1.8v). figure 2-48: 100 k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-49: 100 k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-50: 100 k ? rheo mode ? r w ( ? ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 1.8v). 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.2 -0.1 0 0.1 0.2 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 5000 10000 15000 20000 25000 0 64 128 192 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.35 -0.25 -0.15 -0.05 0.05 0.15 0.25 0.35 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw note: refer to appendix b: ?characteriza- tion data analysis? for additional infor- mation on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (rw) (ohms) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 0 5000 10000 15000 20000 25000 0 64 128 192 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 4 9 14 19 24 29 34 39 44 49 54 59 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl rw note: refer to appendix b: ?characteriza- tion data analysis? for additional infor- mation on the characteristics of the wiper resistance (r w ) with respect to device voltage and wiper setting value. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 28 ? 2008-2013 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-51: 100 k ? ? nominal resistance ( ? ) vs. ambient temperature and v dd . figure 2-52: 100 k ? ? r wb ( ? ) vs. wiper setting and ambient temperature. 98500 99000 99500 100000 100500 101000 101500 102000 102500 103000 103500 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 1.8v 0 20000 40000 60000 80000 100000 120000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) rwb (ohms) -40c 25c 85c 125c downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 29 mcp453x/455x/463x/465x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-53: 100 k ? ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-54: 100 k ? ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-55: 100 k ? ? low-voltage increment wiper settling time (v dd =5.5v) (1 s/div). figure 2-56: 100 k ? ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div). downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 30 ? 2008-2013 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-57: resistor network 0 to resistor network 1 r ab (5 k ? ) mismatch vs. v dd and temperature. figure 2-58: resistor network 0 to resistor network 1 r ab (10 k ? ) mismatch vs. v dd and temperature. figure 2-59: resistor network 0 to resistor network 1 r ab (50 k ? ) mismatch vs. v dd and temperature. figure 2-60: resistor network 0 to resistor network 1 r ab (100 k ? ) mismatch vs. v dd and temperature. 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -40 0 40 80 120 temperature (c) % 5.5v 3.0v -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -40 0 40 80 120 temperature (c) % 5.5v 3.0v 0 0.02 0.04 0.06 0.08 0.1 0.12 -40 0 40 80 120 temperature (c) % 5.5v 3.0v -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -40 10 60 110 temperature (c) % 5.5v 3.0v downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 31 mcp453x/455x/463x/465x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-61: v ih (sda, scl) vs. v dd and temperature. figure 2-62: v il (sda, scl) vs. v dd and temperature. figure 2-63: v ol (sda) vs. v dd and temperature (i ol = 3 ma). 1 1.5 2 2.5 3 3.5 4 -40 0 40 80 120 temperature (c) v ih (v) 5.5v 2.7v 1 1.5 2 -40 0 40 80 120 temperature (c) v il (v) 5.5v 2.7v 50 70 90 110 130 150 170 190 210 230 -40 0 40 80 120 temperature (c) v ol (mv) 5.5v 2.7v downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 32 ? 2008-2013 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-64: por/bor trip point vs. v dd and temperature. 2.1 test circuits figure 2-65: -3 db gain vs. frequency test. figure 2-66: r bw and r w measurement. 0 0.2 0.4 0.6 0.8 1 1.2 -40 0 40 80 120 temperature (c) v dd (v) 2.7v 5.5v + - v out 2.5v dc +5v ab w offset gnd v in ab w i w v w floating r bw = v w /i w v a v b r w = (v w -v a )/i w downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 33 mcp453x/455x/463x/465x 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . additional descriptions of the device pins follows. table 3-1: pinout description for the mcp453x/455x/463x/465x pin weak pull-up/ down ( 1 ) standard function single dual symbol i/o buffer type rheo pot ( 1 ) rheo pot 8l 8l 10l 14l 16l 1 1 1 1 16 hvc/a0 i hv w/st smart high voltage command / address 0 2 2 2 2 1 scl i hv w/st no i 2 c clock input 3 3 3 3 2 sda i/o hv w/st no i 2 c serial data i/o. open drain output 44443 , 4 v ss p ground 5 5 5 p1b a analog no potentiometer 1 terminal b 6 6 6 p1w a analog no potentiometer 1 wiper terminal 7 7 p1a a analog no potentiometer 1 terminal a 5 8 8 p0a a analog no potentiometer 0 terminal a 5 6 7 9 9 p0w a analog no potentiometer 0 wiper terminal 6 7 8 10 10 p0b a analog no potentiometer 0 terminal b 11 11, 12 nc no connection 12 13 a2 i hv w/st smart address 2 7 9 13 14 a1 i hv w/st smart address 1 8 8 10 14 15 v dd p positive power supply input 9 9 11 17 ep exposed pad ( note 2 ) legend: hv w/st = high voltage tolerant input (with schmidtt trigger input) a = analog pins (potentiometer terminals) i = digital input (high z) o = digital output i/o = input / output p = power note 1: the pins smart pull-up shuts off while the pin is forced low. this is done to reduce the standby and sh ut- down current. 2: the dfn and qfn packages have a contact on the bottom of the package. this contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the devices v ss pin. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 34 ? 2008-2013 microchip technology inc. 3.1 high voltage command / address 0 (hvc/a0) the hvc/a0 pin is the address 0 input for the i 2 c interface as well as the high voltage command pin. at the devices por/bor the value of the a0 address bit is latched. this input, along with the a2 and a1 pins, completes the device address. this allows up to eight mcp45xx/46xx devices on a single i 2 c bus. during normal operation the voltage on this pin deter- mines if the i 2 c command is a normal command or a high voltage command (when hvc/a0 = v ihh ). 3.2 serial clock (scl) the scl pin is the serial interfaces serial clock pin. this pin is connected to the host controllers scl pin. the mcp45xx/46xx is a slave device, so its scl pin accepts only external clock signals. 3.3 serial data (sda) the sda pin is the serial interfaces serial data pin. this pin is connected to the host controllers sda pin. the sda pin is an open-drain n-channel driver. 3.4 ground (v ss ) the v ss pin is the device ground reference. 3.5 potentiometer terminal b the terminal b pin is connected to the internal potentiometers terminal b. the potentiometers terminal b is the fixed connection to the zero scale wiper value of the digital potentiome- ter. this corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. the terminal b pin does not have a polarity relative to the terminal w or a pins. the terminal b pin can support both positive and negative current. the voltage on terminal b must be between v ss and v dd . mcp46xx devices have two terminal b pins, one for each resistor network. 3.6 potentiometer wiper (w) terminal the terminal w pin is connected to the internal potenti- ometers terminal w (the wiper). the wiper terminal is the adjustable terminal of the digital potentiometer. the terminal w pin does not have a polarity relative to terminals a or b pins. the terminal w pin can support both positive and negative current. the voltage on terminal w must be between v ss and v dd . mcp46xx devices have two terminal w pins, one for each resistor network. 3.7 potentiometer terminal a the terminal a pin is available on the mcp4xx1 devices, and is connected to the internal potentiome- ters terminal a. the potentiometers terminal a is the fixed connection to the full-scale wiper value of the digital potentiome- ter. this corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. the terminal a pin does not have a polarity relative to the terminal w or b pins. the terminal a pin can support both positive and negative current. the voltage on terminal a must be between v ss and v dd . the terminal a pin is not available on the mcp4xx2 devices, and the internally terminal a signal is floating. mcp46x1 devices have two terminal a pins, one for each resistor network. 3.8 address 2 (a2) the a2 pin is the i 2 c interfaces address 2 pin. along with the a1 and a0 pins, up to eight mcp45xx/46xx devices can be used on a single i 2 c bus. 3.9 address 1 (a1) the a2 pin is the i 2 c interfaces address 1 pin. along with the a2 and a0 pins, up to eight mcp45xx/46xx devices can be used on a single i 2 c bus. 3.10 positive power supply input (v dd ) the v dd pin is the devices positive power supply input. the input power supply is relative to v ss . while the device v dd < v min (2.7v), the electrical performance of the device may not meet the data sheet specifications. 3.11 no connect (nc) these pins should be either connected to v dd or v ss . 3.12 exposed pad (ep) this pad is conductively connected to the devices substrate. this pad should be tied to the same potential as the v ss pin (or left unconnected). this pad could be used to assist as a heat sink for the device when connected to a pcb heat sink. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 35 mcp453x/455x/463x/465x 4.0 functional overview this data sheet covers a family of thirty-two digital potentiometer and rheostat devices that will be referred to as mcp4xxx. the mcp4xx1 devices are the potentiometer configuration, while the mcp4xx2 devices are the rheostat configuration. as the device block diagram shows, there are four main functional blocks. these are: por/bor operation memory map resistor network serial interface (i 2 c) the por/bor operation and the memory map are discussed in this section and the resistor network and i 2 c operation are described in their own sections. the device commands commands are discussed in section 7.0 ?device commands? . 4.1 por/bor operation the power-on reset is the case where the device has power applied to it, starting from the v ss level. the brown-out reset occurs when power is applied to the device, and that power (voltage) drops below the spec- ified range. the devices ram retention voltage (v ram ) is lower than the por/bor voltage trip point (v por /v bor ). the maximum v por /v bor voltage is less than 1.8v. when v por /v bor mcp453x/455x/463x/465x ds22096b-page 36 ? 2008-2013 microchip technology inc. 4.2.1.2 terminal control (tcon) register this register contains 8 control bits. four bits are for wiper 0, and four bits are for wiper 1. register 4-1 describes each bit of the tcon register. the state of each resistor network terminal connection is individually controlled. that is, each terminal connection (a, b and w) can be individually connected/ disconnected from the resistor network. this allows the system to minimize the currents through the digital potentiometer. the value that is written to this register will appear on the resistor network terminals when the serial command has completed. when the wl1 bit is enabled, writes to the tcon register bits r1hw, r1a, r1w, and r1b are inhibited. when the wl0 bit is enabled, writes to the tcon register bits r0hw, r0a, r0w, and r0b are inhibited. on a por/bor this register is loaded with 1ffh (9-bits), for all terminals connected. the host controller needs to detect the por/bor event and then update the volatile tcon register value. additionally, there is a bit which enables the operation of general call commands. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 37 mcp453x/455x/463x/465x register 4-1: tcon bits (address = 0x04) ( 1 ) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 gcen r1hw r1a r1w r1b r0hw r0a r0w r0b bit 8 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 8 gcen: general call enable bit this bit specifies if i 2 c general call commands are accepted 1 = enable device to accept the general call address (0000h) 0 = the general call address is disabled bit 7 r1hw: resistor 1 hardware configuration control bit this bit forces resistor 1 into the shutdown configuration of the hardware pin 1 = resistor 1 is not forced to the hardware pin shutdown configuration 0 = resistor 1 is forced to the hardware pin shutdown configuration bit 6 r1a: resistor 1 terminal a (p1a pin) connect control bit this bit connects/disconnects the resistor 1 terminal a to the resistor 1 network 1 = p1a pin is connected to the resistor 1 network 0 = p1a pin is disconnected from the resistor 1 network bit 5 r1w: resistor 1 wiper (p1w pin) connect control bit this bit connects/disconnects the resistor 1 wiper to the resistor 1 network 1 = p1w pin is connected to the resistor 1 network 0 = p1w pin is disconnected from the resistor 1 network bit 4 r1b: resistor 1 terminal b (p1b pin) connect control bit this bit connects/disconnects the resistor 1 terminal b to the resistor 1 network 1 = p1b pin is connected to the resistor 1 network 0 = p1b pin is disconnected from the resistor 1 network bit 3 r0hw: resistor 0 hardware configuration control bit this bit forces resistor 0 into the shutdown configuration of the hardware pin 1 = resistor 0 is not forced to the hardware pin shutdown configuration 0 = resistor 0 is forced to the hardware pin shutdown configuration bit 2 r0a: resistor 0 terminal a (p0a pin) connect control bit this bit connects/disconnects the resistor 0 terminal a to the resistor 0 network 1 = p0a pin is connected to the resistor 0 network 0 = p0a pin is disconnected from the resistor 0 network bit 1 r0w: resistor 0 wiper (p0w pin) connect control bit this bit connects/disconnects the resistor 0 wiper to the resistor 0 network 1 = p0w pin is connected to the resistor 0 network 0 = p0w pin is disconnected from the resistor 0 network bit 0 r0b: resistor 0 terminal b (p0b pin) connect control bit this bit connects/disconnects the resistor 0 terminal b to the resistor 0 network 1 = p0b pin is connected to the resistor 0 network 0 = p0b pin is disconnected from the resistor 0 network note 1: these bits do not affect the wiper register values. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 38 ? 2008-2013 microchip technology inc. notes: downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 39 mcp453x/455x/463x/465x 5.0 resistor network the resistor network has either 7-bit or 8-bit resolution. each resistor network allows zero scale to full-scale connections. figure 5-1 shows a block diagram for the resistive network of a device. the resistor network is made up of several parts. these include: resistor ladder wiper shutdown (terminal connections) devices have either one or two resistor networks, these are referred to as pot 0 and pot 1. figure 5-1: resistor block diagram. 5.1 resistor ladder module the resistor ladder is a series of equal value resistors (r s ) with a connection point (tap) between the two resistors. the total number of resistors in the series (ladder) determines the r ab resistance (see figure 5-1 ). the end points of the resistor ladder are connected to analog switches, which are connected to the device terminal a and terminal b pins. the r ab (and r s ) resistance has small variations over voltage and temperature. for an 8-bit device, there are 256 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 256 resistors, thus provid- ing 257 possible settings (including terminal a and ter- minal b). for a 7-bit device, there are 128 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 128 resistors, thus provid- ing 129 possible settings (including terminal a and ter- minal b). equation 5-1 shows the calculation for the step resistance. equation 5-1: r s calculation r s a r s r s r s b 256 255 254 10 r w ( 1 ) w (01h) analog mux r w ( 1 ) (00h) r w ( 1 ) (feh) r w ( 1 ) (ffh) r w ( 1 ) (100h) note 1: the wiper resistance is dependent on several factors including, wiper code, device v dd , terminal voltages (on a, b, and w), and temperature. also for the same conditions, each tap selection resistance has a small variation. this r w variation has greater effects on some specifications (such as inl) for the smaller resistance devices (5.0 k ? ) compared to larger resistance devices (100.0 k ? ). r ab 8-bit n = 128 127 126 10 (01h) (00h) (7eh) (7fh) (80h) 7-bit n = r s r ab 256 ?? ------------- = r s r ab 128 ?? ------------- - = 8-bit device 7-bit device downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 40 ? 2008-2013 microchip technology inc. 5.2 wiper each tap point (between the r s resistors) is a connection point for an analog switch. the opposite side of the analog switch is connected to a common signal, which is connected to the terminal w (wiper) pin. a value in the volatile wiper register selects which analog switch to close, connecting the w terminal to the selected node of the resistor ladder. the wiper can connect directly to terminal b or to terminal a. a zero-scale connection, connects the ter- minal w (wiper) to terminal b (wiper setting of 000h). a full-scale connection, connects the terminal w (wiper) to terminal a (wiper setting of 100h or 80h). in these configurations, the only resistance between terminal w and the other terminal (a or b) is that of the analog switches. a wiper setting value greater than full-scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a full-scale setting (terminal w (wiper) connected to terminal a). ta b l e 5 - 1 illustrates the full wiper setting map. equation 5-2 illustrates the calculation used to deter- mine the resistance between the wiper and terminal b. equation 5-2: r wb calculation table 5-1: volatile wiper value vs. wiper position map a por/bor event will load the volatile wiper register value with the default value. table 5-2 shows the default values offered. custom por/bor options are available. contact the local microchip sales office. r wb r ab n 256 ?? ------------- -r w + = n = 0 to 256 (decimal) r wb r ab n 128 ?? ------------- -r w + = n = 0 to 128 (decimal) 8-bit device 7-bit device wiper setting properties 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)), increment and decrement commands ignored 080h 100h full-scale (w = a), increment commands ignored 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) decrement command ignored table 5-2: default factory settings selection resistance code typical r ab value default por wiper setting wiper code 8-bit 7-bit -502 5.0 k ? mid-scale 80h 40h -103 10.0 k ? mid-scale 80h 40h -503 50.0 k ? mid-scale 80h 40h -104 100.0 k ? mid-scale 80h 40h downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 41 mcp453x/455x/463x/465x 5.3 shutdown shutdown is used to minimize the devices current consumption. the mcp4xxx achieves this through the terminal control register (tcon) . 5.3.1 terminal control register (tcon) the terminal control (tcon) register is a volatile register used to configure the connection of each resistor network terminal pin (a, b, and w) to the resistor network. this bits are described in register 4-1 . when the rxhw bit is a 0 , the selected resistor net- work is forced into the following state: the pxa terminal is disconnected the pxw terminal is simultaneously connected to the pxb terminal (see figure 5-2 ) the serial interface is not disabled, and all serial interface activity is executed alternate low power configurations may be achieved with the rxa, rxw, and rxb bits. figure 5-2: resistor network shutdown configuration. 5.3.2 interaction of rxhw bit and rxa, rxw, and rxb bits (tcon register) using the tcon bits allows each resistor network (pot 0 and pot 1) to be individually shutdown. the state of the rxhw bit does not corrupt the other bit values in the tcon register, nor the value of the volatile wiper registers. when the shutdown mode is exited (rxhw changes state from 0 to 1 ): the device returns to the wiper setting specified by the volatile wiper value the rxa, rxb, and rxw bits return to controlling the terminal connection state of that resistor net- work note 1: the rxhw bits are identical to the rxhw bits of the mcp41xx/42xx devices. the mcp42xx devices also have a s hdn pin which forces the resistor network into the same state as that resistor networks rxhw bit. 2: when rxhw = 0 , the state of the tcon register rxa, rxw, and rxb bits is over- ridden (ignored). when the state of the rxhw bit returns to 1 , the tcon register rxa, rxw, and rxb bits return to controlling the terminal connection state. in other words, the rxhw bit does not corrupt the state of the rxa, rxw, and rxb bits. a b w resistor network downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 42 ? 2008-2013 microchip technology inc. notes: downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 43 mcp453x/455x/463x/465x 6.0 serial interface (i 2 c) the mcp45xx/46xx devices support the i 2 c serial protocol. the mcp45xx/46xx i 2 cs module operates in slave mode (does not generate the serial clock). figure 6-1 shows a typical i 2 c interface connection. all i 2 c interface signals are high-voltage tolerant. the mcp45xx/46xx devices use the two-wire i 2 c serial interface. this interface can operate in standard, fast or high-speed mode. a device that sends data onto the bus is defined as transmitter, and a device receiving data, as receiver. the bus has to be con- trolled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions. the mcp45xx/46xx device works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. communi- cation is initiated by the master (microcontroller) which sends the start bit, followed by the slave address byte. the first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the r/w bit. refer to the phillips i 2 c document for more details of the i 2 c specifications. figure 6-1: typical i 2 c interface block diagram. 6.1 signal descriptions the i 2 c interface uses up to five pins (signals). these are: sda (serial data) scl (serial clock) a0 (address 0 bit) a1 (address 1 bit) a2 (address 2 bit) 6.1.1 serial data (sda) the serial data (sda) signal is the data signal of the device. the value on this pin is latched on the rising edge of the scl signal when the signal is an input. with the exception of the start and stop conditions, the high or low state of the sda pin can only change when the clock signal on the scl pin is low. during the high period of the clock the sda pins value (high or low) must be stable. changes in the sda pins value while the scl pin is high will be interpreted as a start or a stop condition. 6.1.2 serial clock (scl) the serial clock (scl) signal is the clock signal of the device. the rising edge of the scl signal latches the value on the sda pin. the mcp45xx/46xx supports three i 2 c interface clock modes: standard mode: clock rates up to 100 khz fast mode: clock rates up to 400 khz high-speed mode (hs mode): clock rates up to 3.4 mhz the mcp4xxx will not stretch the clock signal (scl) since memory read accesses occur fast enough. depending on the clock rate mode, the interface will display different characteristics. 6.1.3 the address bits (a2:a1:a0) there are up to three hardware pins used to specify the device address. the number of address pins is determined by the part number. address 0 is multiplexed with the high voltage command (hvc) function. so the state of a0 is latched on the mcp4xxxs por/bor event. the state of the a2 and a1 pins should be static, that is they should be tied high or tied low. 6.1.3.1 the high voltage command (hvc) signal the high voltage command (hvc) signal is multi- plexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. high voltage commands are sup- ported for compatibility with the nonvolatile devices. the hvc pin has an internal resistor connection to the mcp45xx/46xxs internal v dd signal. scl scl mcp4xxx sda sda hvc/a0 ( 2 ) i/o ( 1 ) host controller typical i 2 c interface connections note 1: if high voltage commands are desired, some type of external circuitry needs to be implemented. 2: these pins have internal pull-ups. if faster rise times are required, then external pull-ups should be added. 3: this pin could be tied high, low, or connected to an i/o pin of the host controller. a1 ( 2 , 3 ) a2 ( 2 , 3 ) downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 44 ? 2008-2013 microchip technology inc. 6.2 i 2 c operation the mcp45xx/46xxs i 2 c module is compatible with the philips i 2 c specification. the following lists some of the modules features: 7-bit slave addressing supports three clock rate modes: - standard mode, clock rates up to 100 khz - fast mode, clock rates up to 400 khz - high-speed mode (hs mode), clock rates up to 3.4 mhz support multi-master applications general call addressing internal weak pull-ups on interface signals the i 2 c 10-bit addressing mode is not supported. the philips i 2 c specification only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of the device. the frame content for the mcp4xxx is defined in section 7.0 . 6.2.1 i 2 c bit states and sequence figure 6-8 shows the i 2 c transfer sequence. the serial clock is generated by the master. the following definitions are used for the bit states: start bit (s) data bit acknowledge (a) bit (driven low) / no acknowledge (a ) bit (not driven low) repeated start bit (sr) stop bit (p) 6.2.1.1 start bit the start bit (see figure 6-2 ) indicates the beginning of a data transfer sequence. the start bit is defined as the sda signal falling when the scl signal is high. figure 6-2: start bit. 6.2.1.2 data bit the sda signal may change state while the scl signal is low. while the scl signal is high, the sda signal must be stable (see figure 6-5 ). figure 6-3: data bit. 6.2.1.3 acknowledge (a) bit the a bit (see figure 6-4 ) is typically a response from the receiving device to the transmitting device. depending on the context of the transfer sequence, the a bit may indicate different things. typically, the slave device will supply an a response after the start bit and 8 data bits have been received. the a bit has the sda signal low. figure 6-4: acknowledge waveform. not a (a ) response the a bit has the sda signal high. table 6-1 shows some of the conditions where the slave device will issue a not a (a ). if an error condition occurs (such as an a instead of a), then an start bit must be issued to reset the command state machine. table 6-1: mcp45xx/46xx a / a responses sdascl s 1st bit 2nd bit sdascl data bit 1st bit 2nd bit event acknowledge bit response comment general call a only if gcen bit is set slave address valid a slave address not valid a device mem- ory address and specified command (ad3:ad0 and c1:c0) are an invalid combi- nation a after device has received address and command bus collision n.a. i 2 c module resets, or a dont care if the colli- sion occurs on the masters start bit. a 8 d0 9 sda scl downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 45 mcp453x/455x/463x/465x 6.2.1.4 repeated start bit the repeated start bit (see figure 6-5 ) indicates the current master device wishes to continue communicat- ing with the current slave device without releasing the i 2 c bus. the repeated start condition is the same as the start condition, except that the repeated start bit follows a start bit (with the data bits + a bit) and not a stop bit. the start bit is the beginning of a data transfer sequence and is defined as the sda signal falling when the scl signal is high. figure 6-5: repeat start condition waveform. 6.2.1.5 stop bit the stop bit (see figure 6-6 ) indicates the end of the i 2 c data transfer sequence. the stop bit is defined as the sda signal rising when the scl signal is high. a stop bit resets the i 2 c interface of all mcp4xxx devices. figure 6-6: stop condition receive or transmit mode. 6.2.2 clock stretching clock stretching is something that the receiving device can do, to allow additional time to respond to the data that has been received. the mcp4xxx will not stretch the clock signal (scl) since memory read accesses occur fast enough. 6.2.3 aborting a transmission if any part of the i 2 c transmission does not meet the command format, it is aborted. this can be intentionally accomplished with a start or stop condition. this is done so that noisy transmissions (usually an extra start or stop condition) are aborted before they corrupt the device. figure 6-7: typical 8-bit i 2 c waveform format. figure 6-8: i 2 c data states and bit sequence. note 1: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low to high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data " 1 ". sda scl sr = repeated start 1st bit scl sda a / a p 1st bit sdascl s 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit p a / a scl sda start condition stop condition data allowed to change data or a valid downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 46 ? 2008-2013 microchip technology inc. 6.2.4 addressing the address byte is the first byte received following the start condition from the master device. the address contains four (or more) fixed bits and (up to) three user defined hardware address bits (pins a2, a1, and a0). these 7-bits address the desired i 2 c device. the a7:a4 address bits are fixed to 0101 and the device appends the value of following three address pins (a2, a1, a0). address pins that are not present on the device are pulled up (a bit value of 1 ). since there are up to three address bits controlled by hardware pins, there may be up to eight mcp4xxx devices on the same i 2 c bus. figure 6-9 shows the slave address byte format, which contains the seven address bits. there is also a read/ write bit. ta b l e 6 - 2 shows the fixed address for each device. hardware address pins the hardware address bits (a2, a1, and a0) correspond to the logic level on the associated address pins. this allows up to eight devices on the bus. these pins have a weak pull-up enabled when the v dd ? 2008-2013 microchip technology inc. ds22096b-page 47 mcp453x/455x/463x/465x 6.2.6 hs mode the i 2 c specification requires that a high-speed mode device must be activated to operate in high-speed (3.4 mbit/s) mode. this is done by the master sending a special address byte following the start bit. this byte is referred to as the high-speed master mode code (hsmmc). the mcp45xx/46xx device does not acknowledge this byte. however, upon receiving this command, the device switches to hs mode. the device can now com- municate at up to 3.4 mbit/s on sda and scl lines. the device will switch out of the hs mode on the next stop condition. the master code is sent as follows: 1. start condition (s) 2. high-speed master mode code ( 0000 1xxx ), the xxx bits are unique to the high-speed (hs) mode master. 3. no acknowledge (a ) after switching to the high-speed mode, the next transferred byte is the i 2 c control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgements. the master device can then either issue a repeated start bit to address a different device (at high-speed), or a stop bit to return to fast/standard bus speed. after the stop bit, any other master device (in a multi-master system) can arbitrate for the i 2 c bus. see figure 6-10 for illustration of hs mode command sequence. for more information on the hs mode, or other i 2 c modes, please refer to the phillips i 2 c specification. 6.2.6.1 slope control the slope control on the sda output is different between the fast/standard speed and the high-speed clock modes of the interface. 6.2.6.2 pulse gobbler the pulse gobbler on the scl pin is automatically adjusted to suppress spikes < 10 ns during hs mode. figure 6-10: hs mode sequence. s a 0 0 0 0 1 x x xb sr a slave address a /a data p s = start bit sr = repeated start bit a = acknowledge bit a = not acknowledge bit r/w = read/write bit r/w p = stop bit (stop condition terminates hs mode) f/s-mode hs-mode hs-mode continues f/s-mode sr a slave address r/w hs select byte control byte command/data byte(s) control byte downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 48 ? 2008-2013 microchip technology inc. 6.2.7 general call the general call is a method that the master device can communicate with all other slave devices. in a multi-master application, the other master devices are operating in slave mode. the general call address has two documented formats. these are shown in figure 6-11 . we have added a mcp45xx/46xx format in this figure as well. this will allow customers to have multiple i 2 c digital potentiometers on the bus and have them operate in a synchronous fashion (analogous to the dac sync pin functionality). if these mcp45xx/46xx 7-bit com- mands conflict with other i 2 c devices on the bus, then the customer will need two i 2 c busses and ensure that the devices are on the correct bus for their desired application functionality. dual pot devices cannot update both pot0 and pot1 from a single command. to address this, there are general call commands for the wiper 0, wiper 1, and the tcon registers. table 6-3 shows the general call commands. three commands are specified by the i 2 c specification and are not applicable to the mcp45xx/46xx (so com- mand is not acknowledged) the mcp45xx/46xx general call commands are acknowledge. any other command is not acknowledged. table 6-3: general call commands note: there is only one general call command per general call control byte (address). any additional general call commands are ignored and not acknowledged. 7-bit command ( 1 , 2 , 3 ) comment 1000 00db write next byte (third byte) to volatile wiper 0 register 1001 00db write next byte (third byte) to volatile wiper 1 register 1100 00db write next byte (third byte) to tcon register 1000 010b or 1000 011b increment wiper 0 register 1001 010b or 1001 011b increment wiper 1 register 1000 100b or 1000 101b decrement wiper 0 register 1001 100b or 1001 101b decrement wiper 1 register note 1: any other code is not acknowledged. these codes may be used by other devices on the i 2 c bus. 2: the 7-bit command always appends a 0 to form 8-bits. . 3: d is the d8 bit for the 9-bit write value. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 49 mcp453x/455x/463x/465x figure 6-11: general call formats. 0 000 s 0000 x xxxx a xx0ap general call address second byte 7-bit command reserved 7-bit commands (by i 2 c specification - philips # 9398 393 40011, ver. 2.1 january 2000) 0000 011 b - reset and write programmable part of slave address by hardware. 0000 010 b - write programmable part of slave address by hardware. 0000 000 b - not allowed mcp45xx/mcp46xx 7-bit commands 1000 01x b - increment wiper 0 register. 1001 01x b - increment wiper 1 register. the following is a microchip extension to this general call format 0 000 s 0000 x xxxx ax d 0 a general call address second byte 7-bit command mcp45xx/mcp46xx 7-bit commands 1000 00d b - write next byte (third byte) to volatile wiper 0 register. 1001 00d b - write next byte (third byte) to volatile wiper 1 register. d dddd dddap third byte the following is a hardware general call format 0 000 s0 0 0 0 x xxxx a xx1a general call address second byte 7-bit command x xxxx xxxap n occurrences of (data + a) this indicates a hardware general call mcp45xx/mcp46xx will ignore this byte and all following bytes (and a ), until 1000 10x b - decrement wiper 0 register. 1001 10x b - decrement wiper 1 register. 1100 00d b - write next byte (third byte) to tcon register. a stop bit (p) is encountered. 0 for general call command downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 50 ? 2008-2013 microchip technology inc. notes: downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 51 mcp453x/455x/463x/465x 7.0 device commands the mcp4xxxs i 2 c command formats are specified in this section. the i 2 c protocol does not specify how commands are formatted. the mcp4xxx supports four basic commands. depending on the location accessed determines the commands that are supported. for the volatile wiper registers, these commands are: write data read data increment data decrement data for the tcon register, these commands are: write data read data these commands have formats for both a single command or continuous commands. these commands are shown in tab l e 7 - 1 . each command has two operational states. these operational states are referred to as: normal serial commands high-voltage serial commands table 7-1: i 2 c commands normal serial commands are those where the hvc pin is driven to v ih or v il . with high-voltage serial com- mands, the hvc pin is driven to v ihh . in each mode, there are four possible commands. table 7-2 shows the supported commands for each memory location. table 7-3 shows an overview of all the device com- mands and their interaction with other device features. 7.1 command byte the mcp4xxxs command byte has three fields: the address, the command operation, and two data bits, (see figure 7-1 ). currently only one of the data bits is defined (d8). the device memory is accessed when the master sends a proper command byte to select the desired operation. the memory location getting accessed is contained in the command bytes ad3:ad0 bits. the action desired is contained in the command bytes c1:c0 bits (see table 7-1 ). c1:c0 determines if the desired memory location will be read, written, incremented (wiper setting +1) or decremented (wiper setting -1). the increment and decrement commands are only valid on the volatile wiper registers. if the address bits and command bits are not a valid combination, then the mcp4xxx will generate a not acknowledge pulse to indicate the invalid combination. the i 2 c master device must then force a start condi- tion to reset the mcp4xxxs 2 c module. d9 and d8 are the most significant bits for the digital potentiometers wiper setting. the 8-bit devices utilize d8 as their msb while the 7-bit devices utilize d7 (from the data byte) as its msb. figure 7-1: command byte format. note: high voltage commands are supported for compatibility with nonvolatile devices in the family. command # of bit clocks ( 1 ) operates on volatile/ nonvolatile memory operation mode write data single 29 both continuous 18n + 11 volatile only read data single 29 both random 48 both continuous 18n + 11 both increment single 20 volatile only continuous 9n + 11 volatile only decrement single 20 volatile only continuous 9n + 11 volatile only note 1: n indicates the number of times the command operation is to be repeated. aa d 3 a d 2 a d 1 a d 0 c 1 c 0 d 9 d 8 a mcp4xxx command byte 00 = write data 01 = increment msbits (data) 10 = decrement 11 = read data command operation bits memory address downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 52 ? 2008-2013 microchip technology inc. table 7-2: memory map and the supported commands address command operation data (10-bits) ( 1 ) comment value function 00h volatile wiper 0 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn increment wiper decrement wiper 01h volatile wiper 1 write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn increment wiper decrement wiper 02h reserved 03h reserved 04h ( 2 ) volatile tcon register write data nn nnnn nnnn read data ( 3 ) nn nnnn nnnn 05h ( 2 ) reserved read data ( 3 ) nn nnnn nnnn maps to nonvolatile mcp45xx/46xx devices status register 06h - 0fh ( 2 ) reserved note 1: the data memory is only 9-bits wide, so the msb is ignored by the device. 2: increment or decrement commands are invalid for these addresses. 3: i 2 c read operation will read 2 bytes, of which the 10-bits of data are contained within. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 53 mcp453x/455x/463x/465x 7.2 data byte only the read command and the write command have data byte(s). the write command concatenates the 8-bits of the data byte with the one data bit (d8) contained in the command byte to form 9-bits of data (d8:d0). the command byte format supports up to 9-bits of data so that the 8-bit resistor network can be set to full-scale (100h or greater). this allows wiper connections to terminal a and to terminal b. the d9 bit is currently unused. 7.3 error condition if the four address bits received (ad3:ad0) and the two command bits received (c1:c0) are a valid combina- tion, the mcp4xxx will acknowledge the i 2 c bus. if the address bits and command bits are an invalid combination, then the mcp4xxx will not acknowledge the i 2 c bus. once an error condition has occurred, any following commands are ignored until the i 2 c bus is reset with a start condition. 7.3.1 aborting a transmission a restart or stop condition in the expected data bit position will abort the current command sequence and data will not be written to the mcp4xxx. table 7-3: commands command name # of bits high voltage (v ihh ) on hvc pin? write data 29 read data 29 increment wiper 20 decrement wiper 20 high voltage write data 29 yes high voltage read data 29 yes high voltage increment wiper 20 yes high voltage decrement wiper 20 yes downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 54 ? 2008-2013 microchip technology inc. 7.4 write data normal and high voltage the write command can be issued to both the volatile and nonvolatile memory locations. the format of the command (see figure 7-2 ), includes the i 2 c control byte, an a bit, the mcp4xxx command byte, an a bit, the mcp4xxx data byte, an a bit, and a stop (or restart) condition. the mcp4xxx generates the a/a bits. a write command to a volatile memory location changes that location after a properly formatted write command and the a/a clock have been received. 7.4.1 single write to volatile memory for volatile memory locations, data is written to the mcp4xxx after every byte transfer (during the acknowledge). if a stop or restart condition is gener- ated during a data transfer (before the a), the data will not be written to the mcp4xxx. after the a bit, the master can initiate the next sequence with a stop or restart condition. refer to figure 7-2 for the byte write sequence. 7.4.2 continuous writes to volatile memory a continuous write mode of operation is possible when writing to the volatile memory registers (address 00h, 01h, and 04h). this continuous write mode allows writes without a stop or restart condition or repeated transmissions of the i 2 c control byte. figure 7-3 shows the sequence for three continuous writes. the writes do not need to be to the same volatile memory address. the sequence ends with the master sending a stop or restart condition. 7.4.3 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage operational state. high voltage commands allow the devices wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp45xx/46xxs internal v dd signal. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 55 mcp453x/455x/463x/465x figure 7-2: i 2 c write sequence. figure 7-3: i 2 c continuous volatile wiper write. control byte write command write data bits 1 010 sa 2 a 1 a 0 0 0 ad ad ad ad a0 x d 8 a d 3 d7 d6 d5 d4 d2 d1 d0 a p 0 1 2 3 fixed address variable address device memory address command write data bits write bit stop bit control byte write command write data bits 1 010 sa 2 a 1 a 0 0 0 a0 x d 8 a d 3 d7 d6 d5 d4 d2 d1 d0 a fixed address variable address device memory address command write data bits write command write data bits 00xd8a d3 d7 d6 d5 d4 d2 d1 d0 a write command write data bits 00xd8a d3 d7 d6 d5 d4 d2 d1 d0 a p write bit ad ad ad ad 0 1 2 3 ad ad ad ad 0 1 2 3 ad ad ad ad 0 1 2 3 note: only functions when writing the volatile wiper registers (ad3:ad0 = 00h, 01h, and 04h) or the tcon register. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 56 ? 2008-2013 microchip technology inc. 7.5 read data normal and high voltage the read command can be issued to both the volatile and nonvolatile memory locations. the format of the command (see figure 7-4 ) includes the start condi- tion, i 2 c control byte (with r/w bit set to 0), a bit, mcp4xxx command byte, a bit, followed by a repeated start bit, i 2 c control byte (with r/w bit set to 1), and the mcp4xxx transmitting the requested data high byte, a bit, the data low byte, the master generating the a , and stop condition. the i 2 c control byte requires the r/w bit equal to a logic one (r/w = 1) to generate a read sequence. the memory location read will be the last address contained in a valid write mcp4xxx command byte or address 00h, if no write operations have occurred since the device was reset (power-on reset or brown-out reset). read operations initially include the same address byte sequence as the write sequence (shown in figure 6-9 ). this sequence is followed by another control byte (including the start condition and acknowledge) with the r/w bit equal to a logic one (r/w = 1) to indicate a read. the mcp4xxx will then transmit the data con- tained in the addressed register. this is followed by the master generating an a bit in preparation for more data, or an a bit followed by a stop. the sequence is ended with the master generating a stop or restart condition. the internal address pointer is maintained. 7.5.1 single read figure 7-4 shows the waveforms for a single read. for single reads, the master sends a stop or restart condition after the data byte is sent from the slave. 7.5.1.1 random read figure 7-5 shows the sequence for a random reads. refer to figure 7-5 for the random byte read sequence. 7.5.2 continuous reads continuous reads allow the devices memory to be read quickly. continuous reads are possible to all mem- ory locations. if a nonvolatile memory write cycle is occurring, then read commands may only access the volatile memory locations. figure 7-6 shows the sequence for three continuous reads. for continuous reads , instead of transmitting a stop or restart condition after the data transfer, the mas- ter reads the next data byte. the sequence ends with the master not acknowledging and then sending a stop or restart. 7.5.3 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. high voltage commands allow the devices wiperlock technology, and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp4xxxs internal v dd signal. 7.5.4 ignoring an i 2 c transmission and falling off the bus the mcp4xxx expects to receive entire, valid i 2 c commands, and will assume any command not defined as a valid command is due to a bus corruption, and will enter a passive high condition on the sda sig- nal. all signals will be ignored until the next valid start condition and control byte are received. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 57 mcp453x/455x/463x/465x figure 7-4: i 2 c read (last memory address accessed). figure 7-5: i 2 c random read. stop bit control byte 1 010 sa 2 a 1 a 0 1 a fixed address variable address read bits p 0 000 0 0 0d8a 1 read bit d3 d7 d6 d5 d4 d2 d1 d0 a 2 read data bits note 1: master device is responsible for a/a signal. if an a signal occurs, the mcp45xx/46xx will abort this transfer and release the bus. 2: the master device will not acknowledge, and the mcp45xx/46xx will release the bus so the master device can generate a stop or repeated start condition. 3: the mcp45xx/46xx retains the last device memory address that it has received. this is the mcp45xx/46xx does not corrupt the device memory address after repeated start or stop conditions. 4: the device memory address pointer defaults to 00h on por and bor conditions. stop bit control byte read command 1 010 sa 2 a 1 a 0 0 1 ad ad ad ad a1 x x a s r 0 1 2 3 fixed address variable address device memory address command control byte read bits p 0 000 0 0 0d8a 1 write bit d3 d7 d6 d5 d4 d2 d1 d0 a 2 1 010 a2a1a01 a read bit repeated start bit read data bits note 1: master device is responsible for a / a signal. if a a signal occurs, the mcp45xx/46xx will abort this transfer and release the bus. 2: the master device will not acknowledge, and the mcp45xx/46xx will release the bus so the master device can generate a stop or repeated start condition. 3: the mcp45xx/46xx retains the last device memory address that it has received. this is the mcp45xx/46xx does not corrupt the device memory address after repeated start or stop conditions. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 58 ? 2008-2013 microchip technology inc. figure 7-6: i 2 c continuous reads. stop bit control byte 1 010 sa 2 a 1 a 0 1 a fixed address variable address read bits 0 000 0 0 0d8a 1 read bit d3 d7 d6 d5 d4 d2 d1 d0 a 1 read data bits 0 000 0 0 0d8a 1 d3 d7 d6 d5 d4 d2 d1 d0 a 1 p 0 000 0 0 0d8a 1 d3 d7 d6 d5 d4 d2 d1 d0 a 2 read data bits read data bits note 1: master device is responsible for a / a signal. if a a signal occurs, the mcp45xx/46xx will abort this transfer and release the bus. 2: the master device will not acknowledge, and the mcp45xx/46xx will release the bus so the master device can generate a stop or repeated start condition. downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 59 mcp453x/455x/463x/465x 7.6 increment wiper normal and high voltage the increment command provides a quick and easy method to modify the potentiometers wiper by +1 with minimal overhead. the increment command will only function on the volatile wiper setting memory locations 00h and 01h. when executing an increment command, the volatile wiper setting will be altered from n to n+1 for each increment command received. the value will incre- ment up to 100h maximum on 8-bit devices, and 80h on 7-bit devices. if multiple increment commands are received after the value has reached 100h (or 80h), the value will not be incremented further. tab l e 7 - 4 shows the increment command versus the current volatile wiper value. refer to figure 7-7 for the increment command sequence. the sequence is terminated by the stop condition. so when executing a continuous command string, the increment command can be followed by any other valid command. this means that writes do not need to be to the same volatile memory address. the advantage of using an increment command instead of a read-modify-write series of commands is speed and simplicity. the wiper will transition after each command acknowledge when accessing the vol- atile wiper registers. table 7-4: increment operation vs. volatile wiper value 7.6.1 the high voltage command (hvc) signal the high voltage command (hvc) signal is multi- plexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. an hvc/a0 pin voltage > v ihh (~8.5v) puts the mcp45xx/46xx device into the high voltage mode. the hvc pin has an internal resistor connection to the mcp45xx/46xxs internal v dd signal. figure 7-7: i 2 c increment command sequence. note: table 7-2 shows the valid addresses for the increment wiper command. other addresses are invalid. note: the command sequence can go from an increment to any other valid command for the specified address. current wiper setting wiper (w) properties increment command operates? 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)) no 080h 100h full-scale (w = a) no 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) yes 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) yes note: there is a required delay after the hvc pin is driven to the v ihh level to the 1st edge of the scl pin. control byte incr command (n+1) incr command (n+2) 1 010 sa 2 a 1 a 0 0 0 ad ad ad ad a1 x x a 0 ad ad ad ad 1x x a p (2) 0 1 2 3 4321 fixed address variable address device memory address command write bit note1: increment command (incr) only functions when accessing the volatile wiper registers (ad3:ad0 = 0h and 1h). 2: this command sequence does not need to terminate (using the stop bit) and can change to any other desired command sequence (increment, read or write). downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 60 ? 2008-2013 microchip technology inc. 7.7 decrement wiper normal and high voltage the decrement command provides a quick and easy method to modify the potentiometers wiper by -1, with minimal overhead. the decrement command will only function on the volatile wiper setting memory locations 00h and 01h. when executing a decrement command, the volatile wiper setting will be altered from n to n-1 for each decrement command received. the value will decrement down to a minimum of 000h. if multiple dec- rement commands are received after the value has reached 000h, the value will not be decremented fur- ther. tab l e 7 - 5 shows the increment command versus the current volatile wiper value. refer to figure 7-8 for the decrement command sequence. the sequence is terminated by the stop condition. so when executing a continuous command string, the increment command can be followed by any other valid command. this means that writes do not need to be to the same volatile memory address. the advantage of using a decrement command instead of a read-modify-write series of commands is speed and simplicity. the wiper will transition after each command acknowledge when accessing the volatile wiper registers. table 7-5: decrement operation vs. volatile wiper value 7.7.1 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. an hvc/a0 pin voltage > v ihh (~8.5v) puts the mcp45xx/46xx device into the high voltage mode. the hvc pin has an internal resistor connection to the mcp45xx/46xxs internal v dd signal. figure 7-8: i 2 c decrement command sequence. note: table 7-2 shows the valid addresses for the decrement wiper command. other addresses are invalid. note: the command sequence can go from an increment to any other valid command for the specified address. current wiper setting wiper (w) properties decrement command operates? 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)) no 080h 100h full-scale (w = a) yes 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) yes 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) no note: there is a required delay after the hvc pin is driven to the v ihh level to the 1st edge of the scl pin. control byte decr command (n-1) decr command (n-2) 1 010 sa 2 a 1 a 0 0 1 ad ad ad ad a0 x x a 1 ad ad ad ad 0x xap (2) 0 1 2 3 4321 fixed address variable address device memory address command write bit note1: decrement command (decr) only functions when accessing the volatile wiper registers (ad3:ad0 = 0h and 1h). 2: this command sequence does not need to terminate (using the stop bit) and can change to any other desired command sequence (incr, read, or write). downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 61 mcp453x/455x/463x/465x 8.0 applications examples nonvolatile digital potentiometers have a multitude of practical uses in modern electronic circuits. the most popular uses include precision calibration of set point thresholds, sensor trimming, lcd bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. the mcp453x/455x/463x/465x devices can be used to replace the common mechani- cal trim pot in applications where the operating and terminal voltages are within cmos process limitations (v dd = 2.7v to 5.5v). 8.1 techniques to force the hvc pin to v ihh the circuit in figure 8-1 shows a method using the tc1240a doubling charge pump. when the shdn pin is high, the tc1240a is off, and the level on the hvc pin is controlled by the pic ? microcontrollers (mcus) io2 pin. when the shdn pin is low, the tc1240a is on and the v out voltage is 2 * v dd . the resistor r 1 allows the hvc pin to go higher than the voltage such that the pic mcus io2 pin clamps at approximately v dd . figure 8-1: using the tc1240a to generate the v ihh voltage. the circuit in figure 8-2 shows the method used on the mcp402x nonvolatile digital potentiometer evaluation board (part number: mcp402xev). this method requires that the system voltage be approximately 5v. this ensures that when the pic10f206 enters a brown-out condition, there is an insufficient voltage level on the hvc pin to change the stored value of the wiper. the mcp402x nonvolatile digital potentiometer evaluation board users guide (ds51546) contains a complete schematic. gp0 is a general purpose i/o pin, while gp2 can either be a general purpose i/o pin or it can output the internal clock. for the serial commands, configure the gp2 pin as an input (high impedance). the output state of the gp0 pin will determine the voltage on the hvc pin (v il or v ih ). for high-voltage serial commands, force the gp0 output pin to output a high level (v oh ), and configure the gp2 pin to output the internal clock. this will form a charge pump and increase the voltage on the hvc pin (when the system voltage is approximately 5v). figure 8-2: mcp4xxx nonvolatile digital potentiometer evaluation board (mcp402xev) implementation to generate the v ihh voltage. hvc pic mcu mcp45xx r 1 io1 io2 c 2 tc1240a v in shdn c+ c- v out c 1 mcp46xx hvc pic10f206 mcp4xxx r 1 gp0 gp2 c 2 c 1 downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 62 ? 2008-2013 microchip technology inc. 8.2 using shutdown figure 8-3 shows a possible application circuit where the independent terminals could be used. disconnect- ing the wiper allows the transistor input to be taken to the bias voltage level (disconnecting a and or b may be desired to reduce system current). disconnecting ter- minal a modifies the transistor input by the r bw rheostat value to the common b. disconnecting terminal b modifies the transistor input by the r aw rheostat value to the common a. the common a and common b connections could be connected to v dd and v ss . figure 8-3: example application circuit using terminal disconnects. 8.3 software reset sequence at times it may become necessary to perform a soft- ware reset sequence to ensure the mcp45xx/46xx device is in a correct and known i 2 c interface state. this technique only resets the i 2 c state machine. this is useful if the mcp45xx/46xx device powers up in an incorrect state (due to excessive bus noise, ...), or if the master device is reset during communication. figure 8-4 shows the communication sequence to soft- ware reset the device. figure 8-4: software reset sequence format. the 1st start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. this occurs since the device is monitor- ing the data bus in receive mode and can detect the start bit which forces an internal reset. the nine bits of 1 are used to force a reset of those devices that could not be reset by the previous start bit. this occurs only if the mcp45xx/46xx is driving an a bit on the i 2 c bus, or is in output mode (from a read command) and is driving a data bit of 0 onto the i 2 c bus. in both of these cases, the previous start bit could not be generated due to the mcp45xx/46xx holding the bus low. by sending out nine 1 bits, it is ensured that the device will see an a bit (the master device does not drive the i 2 c bus low to acknowledge the data sent by the mcp45xx/46xx), which also forces the mcp45xx/46xx to reset. the 2nd start bit is sent to address the rare possibility of an erroneous write. this could occur if the master device was reset while sending a write command to the mcp45xx/46xx, and then as the master device returns to normal operation and issues a start condi- tion, while the mcp45xx/46xx is issuing an acknowl- edge. in this case, if the 2nd start bit is not sent (and the stop bit was sent) the mcp45xx/46xx could initi- ate a write cycle. the stop bit terminates the current i 2 c bus activity. the mcp45xx/46xx wait to detect the next start condition. this sequence does not effect any other i 2 c devices which may be on the bus, as they should disregard this as an invalid command. note: this technique is documented in an1028. balance bias w b input input to base of transistor (or amplifier) a common b common a note: the potential for this erroneous write only occurs if the master device is reset while sending a write command to the mcp45xx/46xx. s 1 1 1 1 1 1 1 1 s p start bit nine bits of 1 start bit stop bit downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 63 mcp453x/455x/463x/465x 8.4 using the general call command the use of the general call address increment, decre- ment, or write commands is analogous to the load feature (ldac pin) on some dacs (such as the mcp4921). this allows all the devices to update the output level at the same time. for some applications, the ability to update the wiper values at the same time may be a requirement, since they delay from writing to one wiper value and then the next may cause application issues. a possible example would be a tuned circuit that uses several mcp45xx/ 46xx in rheostat configuration. as the system condition changes (temperature, load, ...) these devices need to be changed (incremented/decremented) to adjust for the system change. these changes will either be in the same direction or in opposite directions. with the potentiometer device, the customer can either select the pxb terminals (same direction) or the pxa terminal(s) (opposite direction). figure 8-6 shows that the update of six devices takes 6*t i2cdly time in normal operation, but only 1*t i2cdly time in general call operation. figure 8-5 shows two i 2 c bus configurations. in many cases, the single i 2 c bus configuration will be adequate. for applications that do not want all the mcp45xx/46xx devices to do general call support or have a conflict with general call commands, the multiple i 2 c bus configuration would be used. figure 8-5: typical application i 2 c bus configurations. figure 8-6: example comparison of ?normal operation? vs. ?general call operation? wiper updates. note: the application system may need to partition the i 2 c bus into multiple busses to ensure that the mcp45xx/46xx general call commands do not conflict with the general call commands that the other i 2 c devices may have defined. also if only a portion of the mcp45xx/46xx devices are to require this synchronous operation, then the devices that should not receive these commands should be on the second i 2 c bus. single i 2 c bus configuration host controller device 1 device 3 device n device 2 device 4 multiple i 2 c bus configuration host controller device 1a device 3a device na device 2a device 4a device 1b device 3b device nb device 2b device 4b bus b bus a device 1n device 3n device nn device 2n device 4n bus n normal operation general call operation inc pot01 inc pot02 inc pot03 inc pot04 incpot05 incpot06 t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly = time from one i 2 c command completed to completing the next i 2 c command. inc pots 01-06 inc pots 01-06 inc pots 01-06 inc pots 01-06 inc pots 01-06 inc pots 01-06 t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 64 ? 2008-2013 microchip technology inc. 8.5 implementing log steps with a linear digital potentiometer in audio volume control applications, the use of logarithmic steps is desirable since the human ear hears in a logarithmic manner. the use of a linear potentiometer can approximate a log potentiometer, but with fewer steps. an 8-bit potentiometer can achieve fourteen 3 db log steps plus a 100% (0 db) and a mute setting. figure 8-7 shows a block diagram of one of the mcp45x1 resistor networks being used to attenuate an input signal. in this case, the attenuation will be ground referenced. terminal b can be connected to a common mode voltage, but the voltages on the a, b and wiper terminals must not exceed the mcp45x1s v dd /v ss voltage limits. figure 8-7: signal attenuation block diagram - ground referenced. equation 8-1 shows the equation to calculate voltage db gain ratios for the digital potentiometer, while equation 8-2 shows the equation to calculate resistance db gain ratios. these two equations assume that the b terminal is connected to ground. if terminal b is not directly resistively connected to ground, then this terminal b to ground resistance (r b2gnd ) must be included into the calculation. equation 8-3 shows this equation. equation 8-1: db calculations (voltage) equation 8-2: db calculations (resistance) - case 1 equation 8-3: db calculations (resistance) - case 2 table 8-1 shows the codes that can be used for 8-bit digital potentiometers to implement the log attenuation. the table shows the wiper codes for -3 db, -2 db and -1 db attenuation steps. this table also shows the calculated attenuation based on the wiper codes linear step. calculated attenuation values less than the desired attenuation are shown with red text. at lower wiper code values, the attenuation may skip a step; if this occurs the next attenuation value is colored magenta to highlight that a skip occurred. for example, in the -3 db column the -48 db value is highlighted since the -45 db step could not be implemented (there are no wiper codes between 2 and 1). p0a p0w p0b mcp45x1 l20 10 v out v in ------------- ?? ?? log ? = db v out / v in ratio -3 0.70795 -2 0.79433 -1 0.89125 terminal b connected to ground (see figure 8-7 ) l20log 10 ? r bw r ab ---------- - ?? ?? = terminal b through r b2gnd to ground l20log 10 r bw r b2gnd + r ab ------------------------------------- - ?? ?? ? = downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 65 mcp453x/455x/463x/465x table 8-1: linear to log attenuation for 8-bit digital potentiometers # of steps -3 db steps -2 db steps -1 db steps desired attenuation wiper code calculated attenuation ( 1 ) desired attenuation wiper code calculated attenuation ( 1 ) desired attenuatio n wiper code calculated attenuation ( 1 ) 0 0 db 256 0 db 0 db 256 0 db 0 db 256 0 db 1 -3 db 181 -3.011 db -2 db 203 -2.015 db -1 db 228 -1.006 db 2 -6 db 128 -6.021 db -4 db 162 -3.975 db -2 db 203 -2.015 db 3- 9 d b9 1 -8.984 db -6 db 128 -6.021 db -3 db 181 -3.011 db 4 -12 db 64 -12.041 db -8 db 102 -7.993 db -4 db 162 -3.975 db 5 -15 db 46 -14.910 db -10 db 81 -9.995 db -5 db 144 -4.998 db 6 -18 db 32 -18.062 db -12 db 64 -12.041 db -6 db 128 -6.021 db 7 -21 db 23 -20.930 db -14 db 51 -14.013 db -7 db 114 -7.027 db 8 -24 db 16 -24.082 db -16 db 41 -15.909 db -8 db 102 -7.993 db 9 -27 db 11 -27.337 db -18 db 32 -18.062 db -9 db 91 -8.984 db 10 -30 db 8 -30.103 db -20 db 26 -19.865 db -10 db 81 -9.995 db 11 -33 db 6 -32.602 db -22 db 20 -22.144 db -11 db 72 -11.018 db 12 -36 db 4 -36.124 db -24 db 16 -24.082 db -12 db 64 -12.041 db 13 -39 db 3 -38.622 db -26 db 13 -25.886 db -13db 57 -13.047db 14 -42 db 2 -42.144 db -28 db 10 -28.165 db -14 db 51 -14.013 db 15 -48 db 1 -48.165 db -30 db 8 -30.103 db -15 db 46 - 14.910 db 16 mute 0 mute -32 db 6 -32.602 db -16 db 41 -15.909 db 17 -34 db 5 -34.185 db -17 db 36 -17.039 db 18 -36 db 4 -36.124 db -18 db 32 -18.062 db 19 -38 db 3 -38.622 db -19 db 29 -18.917 db 20 -42 db 2 -42.144 db -20 db 26 -19.865 db 21 -48 db 1 -48.165 db -21 db 23 - 20.930 db 22 mute 0 mute -22 db 20 -22.144 db 23 -23db 18 -23.059db 24 -24db 16 -24.082db 25 -25db 14 -25.242db 26 -26 db 13 -25.886 db 27 -27db 11 -27.337 db 28 -28db 10 -28.165db 29 -29db 9 -29.080db 30 -30db 8 -30.103db 31 -31db 7 -31.263db 32 -33 db 6 -32.602 db 33 -34db 5 -34.185db 34 -36 db 4 -36.124 db 35 -39 db 3 -38.622 db 36 -42 db 2 -42.144 db 37 -48 db 1 -48.165 db 38 mute 0 mute note 1: attenuation values do not include errors from digital potentiometer errors, such as full scale error or zero scale error. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 66 ? 2008-2013 microchip technology inc. 8.6 design considerations in the design of a system with the mcp4xxx devices, the following considerations should be taken into account: power supply considerations layout considerations 8.6.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-8 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close (within 4 mm) to the device power pin (v dd ) as possible. the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v dd and v ss should reside on the analog plane. figure 8-8: typical microcontroller connections. 8.6.2 layout considerations inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the mcp4xxxs performance. careful board layout minimizes these effects and increases the signal-to-noise ratio (snr). multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. particularly harsh environ- ments may require shielding of critical signals. if low noise is desired, breadboards and wire-wrapped boards are not recommended. 8.6.3 resistor tempco characterization curves of the resistor temperature coefficient (tempco) are shown in figure 2-12 , figure 2-25 , figure 2-38 , and figure 2-51 . these curves show that the resistor network is designed to correct for the change in resistance as temperature increases. this technique reduces the end-to-end change in r ab resistance. 8.6.4 high voltage tolerant pins high voltage support (v ihh ) on the serial interface pins is for compatibility with the nonvolatile devices. v dd v dd v ss v ss mcp453x/455x/ 463x/465x 0.1 f pic ? microcontroller 0.1 f scl sda w b a downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 67 mcp453x/455x/463x/465x 9.0 device options additional, custom devices are available. these devices have weak pull-up resistors on the sda and scl pins. this is useful for applications where the wiper value is programmed during manufacture and not modified by the system during normal operation. please contact your local sales office for current infor- mation and minimum volume requirements. 9.1 custom options the custom device will have a p (for pull-up) after the resistance version in the product identification system. these devices will not be available through microchips online microchip direct, nor microchips sample sys- tems. example part number: mcp4631-103 p e/st downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 68 ? 2008-2013 microchip technology inc. notes: downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 69 mcp453x/455x/463x/465x 10.0 development support 10.1 development tools several development tools are available to assist in your design and evaluation of the mcp45xx/46xx devices. the currently available tools are shown in table 10-1 . these boards may be purchased directly from the microchip web site at www.microchip.com . 10.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. tab l e 1 0- 2 shows some of these documents. table 10-1: development tools table 10-2: technical documentation board name part # supported devices mcp46xx pictail plus daughter board ( 2 ) mcp46xxdm-ptpls mcp46xx mcp4xxx digital potentiometer daughter board ( 1 ) mcp4xxxdm-db mcp42xxx, mcp42xx, mcp46xx, mcp4021, and mcp4011 mcp46xxev evaluation board mcp46xxev mcp4631, mcp4641, mcp4651, mcp4661 tssop-20 and ssop-20 evaluation board tssop20ev mcp4631, mcp4641, mcp4651, mcp4661 8-pin soic/msop/tssop/dip evaluation board s oic8ev any 8-pin device in dip, soic, msop, or tssop package 14-pin soic/msop/dip evaluation board soic14ev any 14-pin device in dip, soic, or msop package note 1: requires the use of a picdem demo board (see users guide for details) and the soic14ev board to convert an mcp46xx device in tssop package to the dip footprint. 2: requires the use of the pic24 explorer 16 demo board (see users guide for details) application note number title literature # an1316 using digital potentiometers for programmable amplifier gain ds01316 an1080 understanding digital potentiometers resistor variations ds01080 an737 using digital potentiometers to design low pass adjustable filters ds00737 an692 using a digital potentiometer to optimize a precision single supply photo detect ds00692 an691 optimizing the digital potentiometer in precision circuits ds00691 an219 comparing digital potentiometers to mechanical potentiometers ds00219 digital potentiometer design guide ds22017 signal chain design guide ds21825 downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 70 ? 2008-2013 microchip technology inc. notes: downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 71 mcp453x/455x/463x/465x 11.0 packaging information 11.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 8-lead dfn (3x3) example : part number code part number code mcp4531-502e/mf daca mcp4532-502e/mf dace mcp4531-103e/mf dacb mcp4532-103e/mf dacf mcp4531-104e/mf dacd mcp4532-104e/mf dach mcp4531-503e/mf dacc mcp4532-503e/mf dacg mcp4551-502e/mf dact mcp4552-502e/mf dacx mcp4551-103e/mf dacu mcp4552-103e/mf dacy mcp4551-104e/mf dacw mcp4552-104e/mf dada mcp4551-503e/mf dacv mcp4552-503e/mf dacz daca 1028 256 xxxx xyww nnn 8-lead msop xxxxxx ywwnnn example 453113 028256 part number code part number code mcp4531-103e/ms 453113 mcp4532-103e/ms 453213 mcp4531-104e/ms 453114 mcp4532-104e/ms 453214 mcp4531-502e/ms 453152 mcp4532-502e/ms 453252 mcp4531-503e/ms 453153 mcp4532-503e/ms 453253 mcp4551-103e/ms 455113 mcp4552-103e/ms 455213 mcp4551-104e/ms 455114 mcp4552-104e/ms 455214 mcp4551-502e/ms 455152 mcp4552-502e/ms 455252 mcp4551-503e/ms 455153 mcp4552-503e/ms 455253 downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 72 ? 2008-2013 microchip technology inc. package marking information (continued) 10-lead dfn (3x3) example : part number code part number code mcp4632-502e/mf aaba mcp4652-502e/mf aaka mcp4632-103e/mf aaca mcp4652-103e/mf aala mcp4632-104e/mf aaea mcp4652-104e/mf aapa mcp4632-503e/mf aada mcp4652-503e/mf aama aafa 1028 256 xxxx yyww nnn 10-lead msop xxxxxx ywwnnn example 463252 028256 part number code part number code mcp4632-502e/un 463252 mcp4652-502e/un 465252 mcp4632-103e/un 463213 mcp4652-103e/un 465213 mcp4632-104e/un 463214 mcp4652-104e/un 465214 mcp4632-503e/un 463253 mcp4652-503e/un 465253 14-lead tssop (mcp4631, mcp4651) xxxxxxxx yyww nnn example 4631502e 1028 256 xxxxx 16-lead qfn (mcp4631, mcp4651) xxxxxx yywwnnn example xxxxxx 4631 502 028256 e/ml^^ 3 e downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 73 mcp453x/455x/463x/465x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 74 ? 2008-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 75 mcp453x/455x/463x/465x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 76 ? 2008-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 77 mcp453x/455x/463x/465x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 78 ? 2008-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 79 mcp453x/455x/463x/465x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 80 ? 2008-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 81 mcp453x/455x/463x/465x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 82 ? 2008-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging un downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 83 mcp453x/455x/463x/465x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging un downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 84 ? 2008-2013 microchip technology inc. 10-lead plastic micro small outline package (un) [msop] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 85 mcp453x/455x/463x/465x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 86 ? 2008-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 87 mcp453x/455x/463x/465x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 88 ? 2008-2013 microchip technology inc. d e n 21 exposed pad d2 e2 2 1 e b k n note 1 a3 a1 a l top view bottom view downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 89 mcp453x/455x/463x/465x note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 90 ? 2008-2013 microchip technology inc. notes: downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 91 mcp453x/455x/463x/465x appendix a: revision history revision b (february 2013) the following is the list of modifications: 1. corrected mcp45x1 dfn package pinout. 2. corrected device block diagram . 3. updated the absolute maximum ratings ? with total power dissipation values for each package type. 4. updated typical thermal values in temperature characteristics table. 5. corrected labeling in figure 2-1 , from section 2.0 ?typical performance curves? . also corrected figure 2-4 . 6. appropriate 1.8v graphs in section 2.0 ?typi- cal performance curves? now reference appendix b: ?characterization data analy- sis? . 7. added new figure 2-66 . 8. corrected values in figure 5-1 . 9. added description of wiper value on por/bor ( section 5.2 ?wiper? ). 10. added new section section 8.5 ?implementing log steps with a linear digital potentiometer? . 11. added information in the development tools section ( section 10.0 ?development support? ). 12. updated packaging section with package available landing pattern diagrams. 13. added appendix b: ?characterization data analysis? . 14. updated the format of the absolute maximum ratings ? page in section 1.0 ?electrical characteristics? . 15. clarified actions of the por in section 4.1.1 ?power-on reset? . 16. removed note 3 from tab l e 1 0- 1 . revision a (november 2008) original release of this document. downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 92 ? 2008-2013 microchip technology inc. notes: downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 93 mcp453x/455x/463x/465x appendix b: characterization data analysis some designers may desire to understand the device operational characteristics outside of the specified operating conditions of the device. applications where the knowledge of the resistor network characteristics could be useful include battery powered devices and applications that experience brown-out conditions. in battery applications, the application voltage decays over time until new batteries are installed. as the voltage decays, the system will continue to operate. at some voltage level, the application will be below its specified operating voltage range. this is dependent on the individual components used in the design. it is still useful to understand the device characteristics to expect when this low-voltage range is encountered. unlike a microcontroller, which can use an external supervisor device to force the controller into the reset state, a digital potentiometers resistance characteristic is not specified. but understanding the operational characteristics can be important in the design of the applications circuit for this low-voltage condition. other application system scenarios, where under- standing the low-voltage characteristics of the resistor network could be important, is for system brown-out conditions. for the mcp453x/455x/463x/465x devices, the ana- log operation is specified at a minimum of 2.7v. device testing has terminal a connected to the device v dd (for potentiometer configuration only) and terminal b connected to v ss . b.1 low-voltage operation this appendix gives an overview of cmos semiconductor characteristics at lower voltages. this is important so that the 1.8v resistor network characterization graphs of the mcp453x/455x/463x/ 465x devices can be better understood. for this discussion, we will use the 5 k ? device data. this data was chosen since the variations of wiper resistance has much greater implications for devices with smaller r ab resistances. figure b-1 shows the worst case r bw error from the average r bw as a percentage, while figure b-2 shows the r bw resistance versus wiper code graph. nonlinear behavior occurs at approximately wiper code 160. this is better shown in figure b-2 , where the r bw resistance changes from a linear slope. this change is due to the change in the wiper resistance. figure b-1: 1.8v worst case r bw error from average r bw (r bw0 -r bw3 ) vs. wiper code and temperature (v dd = 1.8v, i w = 190 a). figure b-2: r bw vs. wiper code and temperature (v dd = 1.8v, i w = 190 a). -7.00% -6.00% -5.00% -4.00% -3.00% -2.00% -1.00% 0.00% 1.00% 2.00% 0 32 64 96 128 160 192 224 256 wiper code error % -40c +25c +85c +125c 0 1000 2000 3000 4000 5000 6000 7000 0 32 64 96 128 160 192 224 256 wiper code resistance () -40c +25c +85c +125c downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 94 ? 2008-2013 microchip technology inc. figure b-3 and figure b-4 show the wiper resistance for v dd voltages of 5.5, 3.0, 1.8 volts. these graphs show that as the resistor ladder wiper node voltage (v wcn ) approaches the v dd /2 voltage, the wiper resistance increases. these graphs also show the different resistance characteristics of the nmos and pmos transistors that make up the wiper switch. this is demonstrated by the wiper code resistance curve, which does not mirror itself around the mid-scale code (wiper code = 128). so why are the r w graphs showing the maximum resistance at about mid-scale (wiper code = 128) and the r bw graphs showing the issue at code 160? this requires understanding low-voltage transistor characteristics as well as how the data was measured. figure b-3: wiper resistance (r w ) vs. wiper code and temperature (v dd = 5.5v, i w = 900 ua; v dd = 3.0v, i w = 480 a). figure b-4: wiper resistance (r w ) vs. wiper code and temperature (v dd = 1.8v, i w = 260 a). the method in which the data was collected is important to understand. figure b-5 shows the technique that was used to measure the r bw and r w resistance. in this technique, terminal a is floating and terminal b is connected to ground. a fixed current is then forced into the wiper (i w ), and the corresponding wiper voltage (v w ) is measured. forcing a known current through r bw (i w ) and then measuring the voltage difference between the wiper (v w ) and terminal a (v a ), the wiper resistance (r w ) can be calculated, as shown in figure b-5 . changes in i w cur- rent will change the wiper voltage (v w ). this may effect the devices wiper resistance (r w ). figure b-5: r bw and r w measurement. figure b-6 shows a block diagram of the resistor network where the r ab resistor is a series of 256 r s resistors. these resistors are polysilicon devices. each wiper switch is an analog switch made up of an nmos and pmos transistor. a more detailed figure of the wiper switch is shown in figure b-7 . the wiper resistance is influenced by the voltage on the wiper switches nodes (v g , v w and v wcn ). temperature also influences the characteristics of the wiper switch, as shown in figure b-4 . the nmos transistor and pmos transistor have different characteristics. these characteristics, as well as the wiper switch node voltages, determine the r w resistance at each wiper code. the variation of each wiper switchs characteristics in the resistor network is greater then the variation of the r s resistors. the voltage on the resistor network node (v wcn ) is dependent upon the wiper code selected and the voltages applied to v a , v b and v w . the wiper switch v g voltage to v w or v wcn voltage determines how strongly the transistor is turned on. when the transistor is weakly turned on the wiper resistance, r w will be high. when the transistor is strongly turned on, the wiper resistance (r w ) will be in the typical range. 20 40 60 80 100 120 140 160 180 200 220 0 64 128 192 256 wiper code resistance () -40c @ 3.0v +25c @ 3.0v +85c @ 3.0v +125c @ 3.0v -40c @5.5v +25c @ 5.5v +85c @ 5.5v +125c @ 5.5v 20 520 1020 1520 2020 0 64 128 192 256 wiper code resistance () -40c @ 1.8v +25c @ 1.8v +85c @ 1.8v +125c @ 1.8v ab w i w v w floating r bw = v w /i w v a v b r w = (v w -v a )/i w downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 95 mcp453x/455x/463x/465x figure b-6: resistor network block diagram. the characteristics of the wiper are determined by the characteristics of the wiper switch at each of the resistor networks tap points. figure b-7 shows an example of a wiper switch. as the device operational voltage becomes lower, the characteristics of the wiper switch change due to a lower voltage on the v g signal. figure b-7 shows an implementation of a wiper switch. when the transistor is turned off, the switch resistance is in the giga ? s. when the transistor is turned on, the switch resistance is dependent on the v g , v w and v wcn voltages. this resistance is referred to as r w . figure b-7: wiper switch. so, looking at the wiper voltage (v w ) for the 3.0v and 1.8v data gives the graphs in figure b-8 and figure b-9 . in the 1.8v graph, as the v w approaches 0.8v, the voltage increases nonlinearly. since v = i * r, and the current (i w ) is constant, it means that the device resistance increased nonlinearly at around wiper code 160. figure b-8: wiper voltage (v w ) vs. wiper code (v dd = 3.0v, i w = 190 a). figure b-9: wiper voltage (v w ) vs. wiper code (v dd = 1.8v, i w = 190 a). r s a r s r s r s b r w (1) w r w (1) r w ( 1 ) r w (1) r w (1) note 1: the wiper resistance is dependent on several factors including, wiper code, device v dd , terminal voltages (on a, b and w), and temperature. r ab nmos pmos n 0 n n-1 n 1 n n n n-2 n n-3 v w v b v a v wc(n-2) dv g note 1: wiper resistance (r w ) depends on the voltages at the wiper switch nodes (v g , v w and v wcn ). r w ( 1 ) nmos pmos n wc wiper v g (v dd /v ss ) gate gate v w v wcn 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 32 64 96 128 160 192 224 256 wiper code wiper voltage (v) -40c +25c +85c +125c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 32 64 96 128 160 192 224 256 wiper code wiper voltage (v) -40c +25c +85c +125c downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 96 ? 2008-2013 microchip technology inc. using the simulation models of the nmos and pmos devices for the mcp4xxx analog switch ( figure b-10 ), we plot the device resistance when the devices are turned on. figure b-11 and figure b-12 show the resistances of the nmos and pmos devices as the v in voltage is increased. the wiper resistance (r w ) is simply the parallel resistance on the nmos and pmos devices (r w = r nmos || r pmos ). below the threshold voltage for the nmos and pmos devices, the resistance becomes very large (giga ? s). in the transistors active region, the resistance is much lower. for these graphs, the resistances are on different scales. figure b-13 and figure b-14 only plot the nmos and pmos device resistance for their active region and the resulting wiper resistance. for these graphs, all resistances are on the same scale. figure b-10: analog switch. figure b-11: nmos and pmos transistor resistance (r nmos , r pmos ) and wiper resistance (r w ) vs. v in (v dd = 3.0v). figure b-12: nmos and pmos transistor resistance (r nmos , r pmos ) and wiper resistance (r w ) vs. v in (v dd = 1.8v). figure b-13: nmos and pmos transistor resistance (r nmos , r pmos ) and wiper resistance (r w ) vs. v in (v dd = 3.0v). figure b-14: nmos and pmos transistor resistance (r nmos , r pmos ) and wiper resistance (r w ) vs. v in (v dd = 1.8v). r w nmos pmos v g (v dd /v ss ) gate gate v out v in 0.00e+00 5.00e+09 1.00e+10 1.50e+10 2.00e+10 2.50e+10 3.00e+10 0.0 0.3 0.6 0.9 1.2 1.5 1.8 v in voltage nmos and pmos resistance () 0 500 1000 1500 2000 2500 wiper resistance () r pmos r nmos r w pmos theshold nmos theshold 0.00e+00 1.00e+09 2.00e+09 3.00e+09 4.00e+09 5.00e+09 6.00e+09 7.00e+09 0.0 0.6 1.2 1.8 2.4 3.0 v in voltage nmos and pmos resistance () 0 20 40 60 80 100 120 140 160 wiper resistance () r pmos r nmos r w pmos theshold nmos theshold 0 50 100 150 200 250 300 0.0 0.6 1.2 1.8 2.4 3.0 v in voltage resistance () r pmos r nmos r w 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0.0 0.3 0.6 0.9 1.2 1.5 1.8 v in voltage resistance () r pmos r nmos r w downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 97 mcp453x/455x/463x/465x b.2 optimizing circuit design for low- voltage characteristics the low-voltage nonlinear characteristics can be minimized by application design. the section will show two application circuits that can be used to control a programmable reference voltage (v out ). minimizing the low-voltage nonlinear characteristics is done by keeping the voltages on the wiper switch nodes at a voltage where either the nmos or pmos transistor is turned on. an example of this is if we are using a digital potentiom- eter for a voltage reference (v out ). lets say that we want v out to range from 0.5 * v dd to 0.6 * v dd . in example implementation #1 ( figure b-15 ), we window the digital potentiometer using resistors r1 and r2. when the wiper code is at full scale, the v out voltage will be ? 0.6 * v dd, and when the wiper code is at zero scale, the v out voltage will be ? 0.5 * v dd . remember that the digital potentiometers r ab variation must be included. tab le b - 1 shows that the v out volt- age can be selected to be between 0.455 * v dd and 0.727 * v dd , which includes the desired range. with respect to the voltages on the resistor network node, at 1.8v the v a voltage would range from 1.29v to 1.31v, while the v b voltage would range from 0.82v to 0.86v. these voltages cause the wiper resistance to be in the nonlinear region (see figure b-12 ). in potentiometer mode, the variation of the wiper resistance is typically not an issue, as shown by the inl/dnl graph ( figure 2-7 ). in example implementation #2 ( figure b-16 ), we use the digital potentiometer in rheostat mode. the resis- tor ladder uses resistors r1 and r2 with r bw at the bottom of the ladder. when the wiper code is at full scale, the v out voltage will be ? 0.6 * v dd , and when the wiper code is at full scale, the v out voltage will be ? 0.5 * v dd . remember that the digital potentiometers r ab variation must be included. ta b l e b - 2 shows that the v out voltage can be selected to be between 0.50 * v dd and 0.687 * v dd , which includes the desired range. with respect to the voltages on the resistor net- work node, at 1.8v the v w voltage would range from 0.29v to 0.38v. these voltages cause the wiper resistance to be in the linear region (see figure b-12 ). figure b-15: example implementation #1. table b-1: example #1 voltage calculations variation min typ max r1 12,000 12,000 12,000 r2 20,000 20,000 20,000 r ab 8,000 10,000 12,000 v out (@ fs) 0.714 v dd 0.70 v dd 0.727 v dd v out (@ zs) 0.476 v dd 0.50 v dd 0.455 v dd v a 0.714 v dd 0.70 v dd 0.727 v dd v b 0.476 v dd 0.50 v dd 0.455 v dd legend: fs C full scale, zs C zero scale ab w v w v a v b r1 r2 v out downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 98 ? 2008-2013 microchip technology inc. figure b-16: example implementation #2. table b-2: example #2 voltage calculations variation min typ max r1 10,000 10,000 10,000 r2 10,000 10,000 10,000 r bw (max) 8,000 10,000 12,000 v out (@ fs) 0.667 v dd 0.643 v dd 0.687 v dd v out (@ zs) 0.50 v dd 0.50 v dd 0.50 v dd v w (@ fs) 0.333 v dd 0.286 v dd 0.375 v dd v w (@ zs) v ss v ss v ss legend: fs C full scale, zs C zero scale ab w v w v a r1 r2 v out v b downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 99 mcp453x/455x/463x/465x product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp4531: single nonvolatile 7-bit potentiometer mcp4531t: single nonvolatile 7-bit potentiometer (tape and reel) mcp4532: single nonvolatile 7-bit rheostat mcp4532t: single nonvolatile 7-bit rheostat (tape and reel) mcp4551: single nonvolatile 8-bit potentiometer mcp4551t: single nonvolatile 8-bit potentiometer (tape and reel) mcp4552: single nonvolatile 8-bit rheostat mcp4552t: single nonvolatile 8-bit rheostat (tape and reel) mcp4631: dual nonvolatile 7-bit potentiometer mcp4631t: dual nonvolatile 7-bit potentiometer (tape and reel) mcp4632: dual nonvolatile 7-bit rheostat mcp4632t: dual nonvolatile 7-bit rheostat (tape and reel) mcp4651: dual nonvolatile 8-bit potentiometer mcp4651t: dual nonvolatile 8-bit potentiometer (tape and reel) mcp4652: dual nonvolatile8-bit rheostat mcp4652t: dual nonvolatile 8-bit rheostat (tape and reel) resistance version: 502 = 5 k ? 103 = 10 k ? 503 = 50 k ? 104 = 100 k ? temperature range: e = -40c to +125c package: mf = plastic dual flat no-lead (3x3 dfn), 8/10-lead ml = plastic quad flat no-lead (qfn), 16-lead ms = plastic micro small outline (msop), 8-lead st = plastic thin shrink small outline (tssop), 14-lead un = plastic micro small outline (msop), 10-lead part no. x /xx package temperature range device examples: a) mcp4531-502e/xx: 5 k ?? 8ld device b) mcp4531-103e/xx: 10 k ? , 8-ld device c) mcp4531-503e/xx: 50 k ? , 8ld device d) mcp4531-104e/xx: 100 k ? , 8ld device e) mcp4531t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4532-502e/xx: 5 k ?? 8ld device b) mcp4532-103e/xx: 10 k ? , 8-ld device c) mcp4532-503e/xx: 50 k ? , 8ld device d) mcp4532-104e/xx: 100 k ? , 8ld device e) mcp4532t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4551-502e/xx: 5 k ?? 8ld device b) mcp4551-103e/xx: 10 k ? , 8-ld device c) mcp4551-503e/xx: 50 k ? , 8ld device d) mcp4551-104e/xx: 100 k ? , 8ld device e) mcp4551t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4552-502e/xx: 5 k ?? 8ld device b) mcp4552-103e/xx: 10 k ? , 8-ld device c) mcp4552-503e/xx: 50 k ? , 8ld device d) mcp4552-104e/xx: 100 k ? , 8ld device e) mcp4552t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4631-502e/xx: 5 k ?? 8ld device b) mcp4631-103e/xx: 10 k ? , 8-ld device c) mcp4631-503e/xx: 50 k ? , 8ld device d) mcp4631-104e/xx: 100 k ? , 8ld device e) mcp4631t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4632-502e/xx: 5 k ?? 8ld device b) mcp4632-103e/xx: 10 k ? , 8-ld device c) mcp4632-503e/xx: 50 k ? , 8ld device d) mcp4632-104e/xx: 100 k ? , 8ld device e) mcp4632t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4651-502e/xx: 5 k ?? 8ld device b) mcp4651-103e/xx: 10 k ? , 8-ld device c) mcp4651-503e/xx: 50 k ? , 8ld device d) mcp4651-104e/xx: 100 k ? , 8ld device e) mcp4651t-104e/xx: t/r, 100 k ? , 8ld device a) mcp4652-502e/xx: 5 k ?? 8ld device b) mcp4652-103e/xx: 10 k ? , 8-ld device c) mcp4652-503e/xx: 50 k ? , 8ld device d) mcp4652-104e/xx: 100 k ? , 8ld device e) mcp4652t-104e/xx: t/r, 100 k ? , 8ld device xx = mf for 8/10-lead 3x3 dfn = ml for 16-lead qfn = ms for 8-lead msop = st for 14-lead tssop = un for 10-lead msop xxx resistance version downloaded from: http:///
mcp453x/455x/463x/465x ds22096b-page 100 ? 2008-2013 microchip technology inc. notes: downloaded from: http:///
? 2008-2013 microchip technology inc. ds22096b-page 101 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2008-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62077-023-8 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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